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4556 Group
SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER
REJ03B0025-0302 Rev.3.02 2006.12.22
DESCRIPTION
The 4556 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with two 8-bit timers (each timer has one or two reload registers), a 16bit timer for clock count, interrupts, and oscillation circuit switch function. The various microcomputers in the 4556 Group include variations of the built-in memory size as shown in the table below.
FEATURES
qMinimum instruction execution time Mask ROM version .............................................................. 0.5 s (at 6 MHz oscillation frequency, in high-speed through-mode) One Time PROM version ................................................... 0.68 s (at 4.4 MHz oscillation frequency, in high-speed through-mode) qSupply voltage Mask ROM version ...................................................... 1.8 to 5.5 V One Time PROM version ............................................. 1.8 to 3.6 V (It depends on operation source clock, oscillation frequency and operation mode)
qTimers Timer 1 ...................................... 8-bit timer with a reload register Timer 2 ................................. 8-bit timer with two reload registers Timer 3 .............................. 16-bit timer (fixed dividing frequency) qInterrupt ........................................................................ 4 sources qKey-on wakeup function pins ..................................................... 9 q LCD control circuit Segment output ........................................................................ 23 Common output .......................................................................... 4 qVoltage drop detection circuit (only H version) Reset occurrence .................................... Typ. 1.8 V (Ta = 25 C) Reset release .......................................... Typ. 1.9 V (Ta = 25 C) qWatchdog timer qClock generating circuit Built-in clock (on-chip oscillator) Main clock (ceramic resonator/RC oscillation) Sub-clock (quartz-crystal oscillation) qLED drive directly enabled (port D)
APPLICATION
Remote control transmitter ROM (PROM) size ( 10 bits) 4096 words 8192 words 8192 words 4096 words 8192 words 8192 words RAM size ( 4 bits) 288 words 288 words 288 words 288 words 288 words 288 words
Part number M34556M4-XXXFP M34556M8-XXXFP M34556G8FP (Note) M34556M4H-XXXFP M34556M8H-XXXFP M34556G8HFP (Note)
Package 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A 42P2R-A
ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM
Note: Shipped in blank.
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4556 Group
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4556 Group
PIN CONFIGURATION
XIN XOUT CNVSS XCIN/D6 XCOUT/D7 RESET COM0 COM1 COM2 COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 20 21 7
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS VDD C/CNTR D5/INT D4 D3 D2 D1 D0 P13/SEG28 P12/SEG27 P11/SEG26 P10/SEG25 P03/SEG24 P02/SEG23 P01/SEG22 P00/SEG21 P23/SEG20 P22/SEG19 P21/SEG18 P20/SEG17
Pin configuration (top view) (4556 Group)
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M34556Mx-XXXFP M34556G8FP M34556MXH-XXXFP M34556G8HFP
4556 Group
4 4 4
Block diagram (4556 Group)
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
I/O por t
Port P0 Port P1 Port P2
Internal peripheral functions
System clock generation circuit XIN -XOUT (Ceramic/RC) XCIN -XCOUT (Quartz-crystal) On-chip oscillator
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Timer
Timer 1(8 bits) Timer 2(8 bits) Timer 3(16 bits)
Watchdog timer (16 bits)
Voltage drop detection circuit
Memory
ROM
4096, 8192 words 10 bits
4500 series CPU core
ALU(4 bits)
Register A (4 bits) Register B (4 bits) Register E (8 bits) Register D (3 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level)
LCD drive control circuit (Max.23 segments 4 common)
RAM
288 words 4 bits LCD display RAM including 23 words 4 bits
Segment output 4
Common output
Port C 1
Port D 2
23
6
Note: The voltage drop detection circuit is equipped with only H version
.
4556 Group
PERFORMANCE OVERVIEW
Parameter Number of basic M34556M4/M8/G8 instructions M34556M4H/M8H/G8H Minimum Mask ROM version instruction execution time One Time PROM version Memory sizes ROM M34556M4 Function 123 124 0.5 s (at 6 MHz oscillation frequency, in through mode) 0.68 s (at 4.4 MHz oscillation frequency, in through mode) 4096 words 10 bits
M34556M4H 8192 words 10 bits M34556M8/G8 M34556M8H/G8H RAM M34556M4/M8/G8 288 words 4 bits (including LCD display RAM 23 words 4 bits) M34556M4H/M8H/G8H Input/Output D0-D5 Six independent I/O ports. I/O ports Input is examined by skip decision. The output structure can be switched by software. Port D5 is also used as INT pin. Two independent output ports. D6, D7 Output Ports D6 and D7 are also used as XCIN and XCOUT, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched P00-P03 I/O by software. Ports P00-P03 are also used as SEG21-SEG24, respectively. 4-bit I/O port; A pull-up function, a key-on wakeup function and output structure can be switched P10-P13 I/O by software. Ports P10-P13 are also used as SEG25-SEG28, respectively. 4-bit I/O port; The output structure can be switched by software. Ports P20-P23 are also used P20-P23 I/O as SEG17-SEG20, respectively. 1-bit output; Port C is also used as CNTR pin. C Output Timers 8-bit programmable timer with a reload register and has an event counter. Timer 1 8-bit programmable timer with two reload registers and PWM output function. Timer 2 16-bit timer, fixed dividing frequency (timer for clock count) Timer 3 4-bit timer with a reload register (for LCD clock) Timer LC 16-bit timer (fixed dividing frequency) (for watchdog) Watchdog timer LCD control Selective bias value 1/2, 1/3 bias circuit 2, 3, 4 duty Selective duty value 4 Common output 23 Segment output 2r 3, 2r 2, r 3, r 2 (r = 80 k, (Ta = 25 C, Typical value)) Internal resistor for power supply Interrupt 4 (one for external, three for timer ) Sources 1 level Nesting Subroutine nesting 8 levels Device structure CMOS silicon gate Package 42-pin plastic molded SSOP (42P2R-A) Operating temperature range -20 C to 85 C Supply 1.8 to 5.5 V (It depends on operation source clock, oscillation frequency and operation mode) Mask ROM version voltage One Time PROM version 1.8 to 3.6 V (It depends on operation source clock, oscillation frequency and operation mode) Power 2.2 mA (at room temperature, VDD = 5 V, f(XIN) = 6 MHz, f(XCIN) = stop, f(RING) = stop, Active mode f(STCK) = f(XIN)/1) (Mask ROM version) dissipation At clock operating mode 6 A (at room temperature, VDD = 5 V, f(XCIN) = 32 kHz) (Typ.value) (Mask ROM version) 0.1 A (at room temperature, VDD = 5 V, output transistor is cut-off state) At RAM back-up (Mask ROM version)
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PIN DESCRIPTION
Pin VDD VSS CNVSS RESET Name Power supply Ground CNVSS Reset input/output Input/Output -- -- -- I/O Function Connected to a plus power supply. Connected to a 0 V power supply. Connect CNVSS to VSS and apply "L" (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the SRST instruction, watchdog timer, the built-in power-on reset or the voltage drop detection circuit causes the system to be reset, the RESET pin outputs "L" level. I/O pins of the main clock generating circuit. When using a ceramic resonator, connect it between pins XIN and XOUT. A feedback resistor is built-in between them. When using the RC oscillation, connect a resistor and a capacitor to XIN, and leave XOUT pin open. I/O pins of the sub-clock generating circuit. Connect a 32.768 kHz quartz-crystal oscillator between pins XCIN and XCOUT. A feedback resistor is built-in between them. XCIN and XCOUT pins are also used as ports D6 and D7, respectively. Each pin of port D has an independent 1-bit wide I/O function. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port D5 is also used as INT pin. Each pin of port D has an independent 1-bit wide output function. The output structure is N-channel open-drain. Ports D6 and D7 are also used as XCIN pin and XCOUT pin, respectively. Port P0 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P0 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P00-P03 are also used as SEG21-SEG24, respectively. Port P1 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Port P1 has a key-on wakeup function and a pull-up function. Both functions can be switched by software. Ports P10-P13 are also used as SEG25-SEG28, respectively. Port P2 serves as a 4-bit I/O port. The output structure can be switched to N-channel open-drain or CMOS by software. For input use, set the latch of the specified bit to "1" and select the N-channel open-drain. Ports P20-P23 are also used as SEG17-SEG20, respectively. 1-bit output port. The output structure is CMOS. Port C is also used as CNTR pin. LCD common output pins. Pins COM0 and COM1 are used at 1/2 duty, pins COM0- COM2 are used at 1/3 duty and pins COM0-COM3 are used at 1/4 duty. LCD segment output pins. SEG0-SEG2 pins are used as VLC3-VLC1 pins, respectively. SEG17-SEG28 pins are used as Ports P20-P23, Ports P00-P03 and Ports P10-P13, respectively. CNTR pin has the function to input the clock for the timer 1 event counter and to output the PWM signal generated by timer 2.CNTR pin is also used as Port C. INT pin accepts external interrupts. They have the key-on wakeup function which can be switched by software. INT pin is also used as Port D5.
XIN XOUT XCIN XCOUT D0-D5
Main clock input Main clock output Sub-clock input Sub-clock output I/O port D Input is examined by skip decision. Output port D
Input Output Input Output I/O
D6, D7
Output
P00-P03
I/O port P0
I/O
P10-P13
I/O port P1
I/O
P20-P23
I/O port P2
I/O
Port C COM0- COM3 SEG0-SEG10 SEG17-SEG28 (Note) CNTR INT
Output port C Common output Segment output
Output Output Output
Timer input/output Interrupt input
I/O Input
Note: SEG11 to SEG16 pins are not existed in the 4556 Group.
MULTIFUNCTION
Pin XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Multifunction D6 D7 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Pin D6 D7 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 Multifunction XCIN XCOUT P00 P01 P02 P03 P10 P11 P12 P13 Pin P20 P21 P22 P23 D5 C SEG0 SEG1 SEG2 Multifunction SEG17 SEG18 SEG19 SEG20 INT CNTR VLC3 VLC2 VLC1 Pin SEG17 SEG18 SEG19 SEG20 INT CNTR VLC3 VLC2 VLC1 Multifunction P20 P21 P22 P23 D5 C SEG0 SEG1 SEG2
Notes 1: Pins except above have just single function. 2: The input/output of D5 can be used even when INT is selected. The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used. 3: The port C "H" output function can be used even when CNTR (output) is selected.
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DEFINITION OF CLOCK AND CYCLE
q Operation source clock The operation source clock is the source clock to operate this product. In this product, the following clocks are used. * Clock (f(XIN)) by the external ceramic resonator * Clock (f(XIN)) by the external RC oscillation * Clock (f(XIN)) by the external input * Clock (f(RING)) of the on-chip oscillator which is the internal oscillator * Clock (f(XCIN)) by the external quartz-crystal resonator Table Selection of system clock Register MR MR2 MR3 MR1 MR0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
q System clock (STCK) The system clock is the basic clock for controlling this product. The system clock is selected by the clock control register MR shown as the table below. q Instruction clock (INSTCK) The instruction clock is the basic clock for controlling CPU. The instruction clock (INSTCK) is a signal derived by dividing the system clock (STCK) by 3. The one instruction clock cycle generates the one machine cycle. q Machine cycle The machine cycle is the standard cycle required to execute the instruction. Operation mode Internal frequency divided by 8 mode Internal frequency divided by 4 mode Internal frequency divided by 2 mode Internal frequency through mode High-speed frequency divided by 8 mode High-speed frequency divided by 4 mode High-speed frequency divided by 2 mode High-speed through mode Low-speed frequency divided by 8 mode Low-speed frequency divided by 4 mode Low-speed frequency divided by 2 mode Low-speed through mode
System clock
f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN)
Note: The f(RING)/8 is selected after system is released from reset.
PORT FUNCTION
Port Port D Pin D0-D4, D5/INT Input Output I/O (6) Output (2) I/O (4) Output structure N-channel open-drain/ CMOS N-channel open-drain N-channel open-drain/ CMOS 4 OP0A IAP0 I/O unit 1 Control Control instructions registers SD, RD FR1, FR2 SZD I1, K2 CLD RG FR0, PU0 K0 C1 FR0, PU1 K0, K1 C2 FR2 L3 W1 Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Built-in pull-up functions, key-on wakeup functions and output structure selection function (programmable) Output structure selection func tion (programmable) Remark Output structure selection function (programmable)
XCIN/D6, XCOUT/D7 Port P0 P00/SEG21-P03/SEG24
Port P1 P10/SEG25-P13/SEG28
I/O (4)
N-channel open-drain/ CMOS
4
OP1A IAP1
Port P2 P20/SEG17-P23/SEG20 Port C C/CNTR
I/O (4) Output (1)
N-channel open-drain/ CMOS CMOS
4 1
OP2A IAP2 RCP SCP
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CONNECTIONS OF UNUSED PINS
Pin XIN XOUT XCIN/D6 XCOUT/D7 D0-D4 D5/INT C/CNTR P00/SEG21- P03/SEG24 Connection Connect to VSS. Open. Connect to VSS. Open. Open. Connect to VSS. Open. Connect to VSS. Open. Open. Connect to VSS. Usage condition RC oscillator is not selected
P10/SEG25- P13/SEG28
Open. Connect to Vss.
N-channel open-drain is selected for the output structure. INT pin input is disabled. N-channel open-drain is selected for the output structure. CNTR input is not selected for timer 1 count source. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. Pull-up transistor is OFF. The key-on wakeup function is invalid. Segment output is not selected. N-channel open-drain is selected for the output structure. SEG0 pin is selected. SEG1 pin is selected. SEG2 pin is selected.
P20/SEG17- P23/SEG20 COM0-COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3-SEG10 (Note)
Open. Connect to Vss. Open. Open. Open. Open. Open.
Note: SEG11 to SEG16 pins are not existed in the 4556 Group.
(Note when connecting to VSS and VDD) q Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise.
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PORT BLOCK DIAGRAMS
Skip decision Register Y Decoder SZD instruction (Note 3) FR1i (Note 1) S SD instruction RD instruction RQ D0--D3 (Note 2) (Note 1)
CLD instruction
Skip decision Register Y Decoder SZD instruction FR20 (Note 1) S SD instruction RD instruction RQ D4 (Note 1) (Note 2)
CLD instruction
Skip decision Register Y Decoder SZD instruction FR21 (Note 1) S SD instruction RD instruction RQ (Note 4) External 0 interrupt Key-on wakeup input Timer 1 count start synchronous circuit input External 0 interrupt circuit D5/INT (Note 2) (Note 1)
CLD instruction
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: i represents bits 0 to 3. 4: As for details, refer to the external interrupt structure.
Port block diagram (1)
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Register Y
Decoder
CLD instruction S SD instruction RD instruction RQ RG2
1 0
(Note 1) XCIN/D6 (Note 2) (Note 1)
Sub-clock input Register Y Decoder
Quartz-crystal oscillation circuit RG2 (Note 1) S RG2 RQ
1 0
CLD instruction SD instruction RD instruction
XCOUT/D7 (Note 2) (Note 1)
Clock input for timer 1 event count Timer 1 underflow signal W41 D T R Q (Note 1) C/CNTR (Note 1) SQ R W10 W11 (Note 2)
W12 PWMOD SCP instruction RCP instruction
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (2)
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LCD power supply LCD control signal
C1j
0 1
(Note 1) P00/SEG21, P01/SEG22 (Note 1) C1j key-on wakeup input K00 Edge detection circuit IAP0 instruction LCD power supply
Register A Aj
FR00
Pull-up transistor PU0j
Aj OP0A instruction
D TQ
LCD power supply LCD control signal
C1k
0 1
(Note 1) P02/SEG23, P03/SEG24 (Note 1) C1k key-on wakeup input K01 Edge detection circuit IAP0 instruction LCD power supply
Register A Ak
FR01
Pull-up transistor PU0K
Ak OP0A instruction
D TQ
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3.
Port block diagram (3)
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LCD power supply LCD control signal
C2j
0 1
(Note 1) P10/SEG25, P11/SEG26 (Note 1) key-on wakeup input K11
0 1
Edge detection circuit Level detection circuit
K10
0
K02
C2j LCD power supply
1
Register A Aj
IAP1 instruction
FR02
Pull-up transistor PU1j
Aj OP1A instruction
D TQ
LCD power supply LCD control signal
C2k
0 1
(Note 1) P12/SEG27, P13/SEG28 (Note 1) K13 key-on wakeup input
0
1
Edge detection circuit Level detection circuit
K12
0 1
K03
C2k LCD power supply
Register A Ak
IAP1 instruction
FR03
Pull-up transistor PU1k
Ak OP1A instruction
D TQ
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3.
Port block diagram (4)
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(Note 3) LCD power supply LCD control signal L3j
0 1
(Note 1) P20/SEG17, P21/SEG18 (Note 2) (Note 1) LCD power supply
(Note 3) L3j (Note 3) Register A Aj FR22 IAP2 instruction
Aj OP2A instruction
D TQ
(Note 4) LCD power supply LCD control signal L3k
0 1
(Note 1) P22/SEG19, P23/SEG20 (Note 2) (Note 1) LCD power supply
(Note 4) L3k (Note 4) Register A Ak FR23 IAP2 instruction
Ak OP2A instruction
D TQ
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less. 3: j represents bits 0 and 1. 4: k represents bits 2 and 3.
Port block diagram (5)
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LCD power supply LCD control signal (Note 1) SEG3-SEG10 (Note 1) LCD control signal LCD power supply LCD power supply LCD control signal (Note 1) COM0-COM3 (Note 2) (Note 2)
(Note 1) LCD control signal LCD power supply LCD power supply LCD control signal
LCD control signal
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (6)
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LCD power supply LCD control signal
L23
1 0
(Note 1) SEG0/VLC3 (Note 2) (Note 1) L23 LCD power supply LCD power supply (VLC3) LCD power supply LCD control signal L22
1 0
(Note 1) SEG1/VLC2 (Note 2) (Note 1) L22 LCD power supply (VLC2) LCD control signal LCD power supply L21
1 0
LCD power supply
L21
(Note 1) SEG2/VLC1 (Note 2) (Note 1)
L21 LCD power supply LCD power supply (VLC1)
L13 L20 Reset signal L12 EPOF+POF2 instruction
Notes 1: This symbol represents a parasitic diode on the port. 2: Applied potential to these ports must be VDD or less.
Port block diagram (7)
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(Note 1) D5/INT (Note 1)
I12
0 1
One-sided edge detection circuit
I11
0 1
Timer 1 count start synchronization circuit input External 0 EXF0 interrupt
Both edges detection circuit
I13
SNZI0 instruction Skip decision K20
Level detection circuit Edge detection circuit
K21
0 1
Key-on wakeup input
*
This symbol represents a parasitic diode on the port.
Block diagram of external interrupt
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FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU)
The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation.
(CY) (M(DP)) Addition (A)
Fig. 1 AMC instruction execution example
ALU
(2) Register A and carry flag
Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation. Carry flag CY is a 1-bit flag that is set to "1" when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A0 is stored in carry flag CY with the RAR instruction (Figure 2). Carry flag CY can be set to "1" with the SC instruction and cleared to "0" with the RC instruction.
SC instruction
RC instruction
CY
A3 A2 A1 A0 RAR instruction
(3) Registers B and E
Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). Register E is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value.
A0
CY A3 A2 A1
Fig. 2 RAR instruction execution example
Register B
TAB instruction
Register A
(4) Register D
Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Also, when the TABP p instruction is executed at UPTF flag = "1", the high-order 2 bits of ROM reference data is stored to the low-order 2 bits of register D, the high-order 1 bit of register D is "0". When the TABP p instruction is executed at UPTF flag = "0", the contents of register D remains unchanged. The UPTF flag is set to "1" with the SUPT instruction and cleared to "0" with the RUPT instruction. The initial value of UPTF flag is "0". Register D is undefined after system is released from reset and returned from the power down mode. Accordingly, set the initial value.
B3 B2 B1 B0
A3 A2 A1 A0
TEAB instruction Register E E7 E6 E5 E4 E3 E2 E1 E0 TABE instruction B3 B2 B1 B0 Register B A3 A2 A1 A0 Register A
TBA instruction
Fig. 3 Registers A, B and register E
TABP p instruction Specifying address
ROM 8 4 0
PCH p6 p5 p4 p3 p2 p1 p0
PCL DR2 DR1DR0 A3 A2 A1 A0
Low-order 4bits Register A (4) Middle-order 4 bits Register B (4)
Immediate field value p
The contents of The contents of register D register A
High-order 2 bits
Register D (3)
* UPTF=1, high-order 1 bit of register D is "0". UPTF=0, data is not transferred to register D.
Fig. 4 TABP p instruction execution example
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(5) Stack registers (SKS) and stack pointer (SP)
Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; * branching to an interrupt service routine (referred to as an interrupt service routine), * performing a subroutine call, or * executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 levels are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call.
Program counter (PC) Executing BM instruction SK0 SK1 SK2 SK3 SK4 SK5 SK6 SK7 Executing RT instruction (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7
Stack pointer (SP) points "7" at reset or returning from power down mode. It points "0" by executing the first BM instruction, and the contents of program counter is stored in SK0. When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK0 is destroyed.
Fig. 5 Stack registers (SKs) structure
(6) Interrupt stack register (SDP)
Interrupt stack register (SDP) is a 1-stage register. When an interrupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and register B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table reference instruction.
(SP) 0 (SK0) 000116 (PC) SUB1
Main program Address 000016 NOP 000116 BM SUB1 000216 NOP
Subroutine
SUB1 : NOP * * * RT
(7) Skip flag
Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt occurs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained.
(PC) (SK0) (SP) 7
Note : Returning to the BM instruction execution address with the RT instruction, and the BM instruction becomes the NOP instruction.
Fig. 6 Example of operation at subroutine call
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(8) Program counter (PC)
Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table reference instruction (TABP p) is executed. Program counter consists of PCH (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which specifies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PCH does not specify after the last page of the built-in ROM.
Program counter p6 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0
PCH Specifying page
PCL Specifying address
Fig. 7 Program counter (PC) structure
Data pointer (DP) Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0
(9) Data pointer (DP)
Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y. Register Z specifies a RAM file group, register X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the power down mode. After system is returned from the power down mode, set these registers.
Register Y (4)
Specifying RAM digit
Register X (4)
Specifying RAM file
Register Z (2)
Specifying RAM file group
Fig. 8 Data pointer (DP) structure
Specifying bit position Set
D3 D2 D1 D0
0
0
0
1
1 Port D output latch
Register Y (4)
Fig. 9 SD instruction execution example
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4556 Group
PROGRAM MEMORY (ROM)
The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34556ED. Table 1 ROM size and pages Part number M34556M4 M34556M4H M34556M8 M34556M8H M34556G8 M34556G8H ROM (PROM) size ( 10 bits) 4096 words 8192 words Pages 32 (0 to 31) 64 (0 to 63)
9876543210 000016 007F16 008016 00FF16 010016 017F16 018016 Page 0 Interrupt address page Subroutine special page Page 1 Page 2 Page 3
1FFF16
Page 63
A part of page 1 (addresses 008016 to 00FF16) is reserved for interrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the instruction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for subroutine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data areas with the TABP p instruction.
Fig. 10 ROM map of M34556M8/M8H/G8/G8H
9 008016 008216 008416 008616 008816 008A16 008C16 008E16
876543210 External 0 interrupt address
Timer 1 interrupt address Timer 2 interrupt address Timer 3 interrupt address
00FF16
Fig. 11 Page 1 (addresses 008016 to 00FF16) structure
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4556 Group
DATA MEMORY (RAM)
1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM (also, set a value after system returns from power down mode). RAM includes the area for LCD. When writing "1" to a bit corresponding to displayed segment, the segment is turned on. Table 2 shows the RAM size. Figure 12 shows the RAM map. * Note Register Z of data pointer is undefined after system is released from reset. Also, registers Z, X and Y are undefined in the RAM back-up. After system is returned from the power down mode, set these registers.
Table 2 RAM size Part number M34556M4/M4H M34556M8/M8H M34556G8/G8H RAM size 288 words 4 bits (1152 bits)
RAM 288 words 4 bits (1152 bits)
Register Z Register X
0
12
0 1 3 ... 12 13 14 15 0 1 2 3
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Register Y
0 8 16 1 9 17 2 10 18 3 11 19 4 12 20 5 13 21 6 14 22 7 15 23
24 25 26 27 28
Note: The numbers in the shaded area indicate the corresponding segment output pin numbers.
Fig. 12 RAM map
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4556 Group
INTERRUPT FUNCTION
The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. * An interrupt activated condition is satisfied (request flag = "1") * Interrupt enable bit is enabled ("1") * Interrupt enable flag is enabled (INTE = "1") Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.)
Table 3 Interrupt sources Priority Interrupt name Activated condition level 1 External 0 interrupt Level change of INT pin 2 Timer 1 interrupt Timer 1 underflow 3 4 Timer 2 interrupt Timer 3 interrupt Timer 2 underflow Timer 3 underflow
Interrupt address Address 0 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1
(1) Interrupt enable flag (INTE)
The interrupt enable flag (INTE) controls whether the every interrupt enable/disable. Interrupts are enabled when INTE flag is set to "1" with the EI instruction and disabled when INTE flag is cleared to "0" with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to "0," so that other interrupts are disabled until the EI instruction is executed. Table 4 Interrupt request flag, interrupt enable bit and skip instruction Interrupt name External 0 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Request flag EXF0 T1F T2F T3F Skip instruction SNZ0 SNZT1 SNZT2 SNZT3 Enable bit V10 V12 V13 V20
(2) Interrupt enable bit
Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function.
Table 5 Interrupt enable bit function Interrupt enable bit 1 0 Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid
(3) Interrupt request flag
When the activated condition for each interrupt is satisfied, the corresponding interrupt request flag is set to "1." Each interrupt request flag is cleared to "0" when either; * an interrupt occurs, or * the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its interrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt disable state is released, the interrupt priority level is as follows shown in Table 3.
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(4) Internal state during an interrupt
The internal state of the microcomputer during an interrupt is as follows (Figure 14). * Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). * Interrupt enable flag (INTE) INTE flag is cleared to "0" so that interrupts are disabled. * Interrupt request flag Only the request flag for the current interrupt source is cleared to "0." * Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP).
* Program counter (PC) ............................................................... Each interrupt address * Stack register (SK) The address of main routine to be .................................................................................................... executed when returning * Interrupt enable flag (INTE) .................................................................. 0 (Interrupt disabled) * Interrupt request flag (only the flag for the current interrupt source) ................................................................................... 0 * Data pointer, carry flag, registers A and B, skip flag ........ Stored in the interrupt stack register (SDP) automatically Fig. 14 Internal state when interrupt occurs
(5) Interrupt processing
When an interrupt occurs, a program at an interrupt address is executed after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an interrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13)
Activated condition INT pin interrupt waveform input
Request flag Enable bit (state retained)
Enable flag
EXF0
V10
Address 0 in page 1
Timer 1 underflow
T1F
V12
Address 4 in page 1
Main routine Interrupt service routine
Interrupt occurs
Timer 2 underflow Timer 3 underflow
T2F
V13
Address 6 in page 1
T3F
V20
INTE
Address 8 in page 1
Fig. 15 Interrupt system diagram * * * *
EI R TI
Interrupt is enabled
: Interrupt enabled state : Interrupt disabled state Fig. 13 Program example of interrupt processing
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4556 Group
(6) Interrupt control registers
* Interrupt control register V1 Interrupt enable bits of external 0, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 6 Interrupt control registers Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1
* Interrupt control register V2 The timer 3 interrupt enable bit is assigned to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A.
at reset : 00002
at power down : 00002
R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid)
Note: "R" represents read enabled, and "W" represents write enabled.
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(7) Interrupt sequence
Interrupts only occur when the respective INTE flag, interrupt enable bits (V10, V12, V13, V20), and interrupt request flag are "1." The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt occurs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
q When an interrupt request flag is set after its interrupt is enabled (Note 1)
1 machine cycle
T1 System clock (STCK)
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
T3
T1
T2
EI instruction execution cycle Interrupt enable flag (INTE) Interrupt enabled state
Interrupt disabled state
INT External interrupt EXF0 Interrupt activated condition is satisfied. Timer 1, Timer 2, Timer 3 interrupts T1F,T2F,T3F
Retaining level of system clock for 4 periods or more is necessary.
Flag cleared 2 to 3 machine cycles (Notes 1, 2) Notes 1: The address is stacked to the last cycle. 2: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied.
The program starts from the interrupt address.
Fig. 16 Interrupt sequence
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4556 Group
EXTERNAL INTERRUPTS
The 4556 Group has the external 0 interrupt. An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupt can be controlled with the interrupt control register I1. Table 7 External interrupt activated conditions Name External 0 interrupt Input pin D5/INT Activated condition When the next waveform is input to D5/INT pin * Falling waveform ("H""L") * Rising waveform ("L""H") * Both rising and falling waveforms Valid waveform selection bit I11 I12
(Note 1) D5/INT
I12
Falling
0 1
Rising
One-sided edge detection circuit
I11
0
EXF0 Both edges detection circuit (Note 2) Level detection circuit K20 (Note 3) Edge detection circuit
1
External 0 interrupt
I13
Timer 1 count start synchronous circuit K21
0
Key-on wakeup
1
Skip decision (SNZI0 instruction)
This symbol represents a parasitic diode on the port. Notes 1: 2: I12 (I22) = 0: "L" level detected I12 (I22) = 1: "H" level detected 3: I12 (I22) = 0: Falling edge detected I12 (I22) = 1: Rising edge detected
Fig. 17 External interrupt circuit structure
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4556 Group
(1) External 0 interrupt request flag (EXF0)
External 0 interrupt request flag (EXF0) is set to "1" when a valid waveform is input to D5/INT pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with the skip instruction. * External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to D5/INT pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. Set the bit 3 of register I1 to "1" for the INT pin to be in the input enabled state. Select the valid waveform with the bits 1 and 2 of register I1. Clear the EXF0 flag to "0" with the SNZ0 instruction. Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. Set both the external 0 interrupt enable bit (V10) and the INTE flag to "1." The external 0 interrupt is now enabled. Now when a valid waveform is input to the D5/INT pin, the EXF0 flag is set to "1" and the external 0 interrupt occurs. Table 8 External interrupt control register Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1
(2) External interrupt control registers
* Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.
at reset : 00002
at power down : state retained
R/W TAI1/TI1A
INT pin input disabled INT pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 2)
I11 I10
INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of these bits (I12 , I13) are changed, the external interrupt request flag (EXF0) may be set.
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(3) Notes on External 0 interrupts
Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 18) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 18). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 18).
Note on bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 20) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 20). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 20).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 18 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of INT pin is not used (register K20 = "0"), clear bits 2 and 3 of register I1 before system enters to the power down mode. (refer to Figure 19).
: these bits are not used here. Fig. 20 External 0 interrupt program example-3
LA 0 TI1A DI EPOF POF2
***
; (002) ; Input of INT disabled ........................
; power down mode
: these bits are not used here. Fig. 19 External 0 interrupt program example-2
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***
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***
4556 Group
TIMERS
The 4556 Group has the following timers. * Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to "1," new data is loaded from the reload register, and count continues (auto-reload function).
* Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency dividing ratio (n). An interrupt request flag is set to "1" after every n count of a count pulse.
FF16 n : Counter initial value Count starts n Reload Reload
The contents of counter
1st underflow
2nd underflow
0016 Time n+1 count Timer interrupt "1" "0" request flag An interrupt occurs or a skip instruction is executed. n+1 count
Fig. 21 Auto-reload function The 4556 Group timer consists of the following circuits. * Prescaler : 8-bit programmable timer * Timer 1 : 8-bit programmable timer * Timer 2 : 8-bit programmable timer * Timer 3 : 16-bit fixed dividing frequency timer * Timer LC : 4-bit programmable timer * Watchdog timer : 16-bit fixed dividing frequency timer (Timers 1, 2, and 3 have the interrupt function, respectively) Prescaler and timers 1, 2, 3 and LC can be controlled with the timer control registers PA, W1 to W4. The watchdog timer is a free counter which is not controlled with the control register. Each function is described below.
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4556 Group
Table 9 Function related timers Circuit Prescaler Timer 1 Structure 8-bit programmable binary down counter 8-bit programmable binary down counter (link to INT input) Count source * Instruction clock (INSTCK) * PWM output (PWMOUT) * Prescaler output (ORCLK) * Timer 3 underflow (T3UDF) * CNTR input Timer 2 8-bit programmable binary down counter (PWM output function) Timer 3 16-bit fixed dividing frequency * XIN input * Prescaler output (ORCLK) divided by 2 * XCIN input * ORCLK 8192 16384 32768 65536 Timer LC Watchdog timer 4-bit programmable binary down counter 16-bit fixed dividing frequency * Bit 4 of timer 3 * System clock (STCK) * Instruction clock (INSTCK) 1 to 16 65534 * LCD clock * System reset (count twice) * WDF flag decision W4 1 to 256 * Timer 1 count source * CNTR output * Timer 2 interrupt * Timer 1 count source * Timer 3 interrupt * Timer LC count source W3 W2 Frequency dividing ratio 1 to 256 1 to 256 Use of output signal * Timer 1, 2, and 3 count sources * CNTR output control * Timer 1 interrupt Control register PA W1
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4556 Group
Division circuit Divided by 8 On-chip oscillator Ceramic resonance MR1, MR0 Multiplexer (CRCK) 00 01 10 Divided by 4 Divided by 2
MR3, MR2 11 10 01 00 Internal clock generating circuit (divided by 3)
System clock (STCK)
Instruction clock (INSTCK)
XIN
RC oscillation
XCIN
Quartz-crystal oscillation PA0 Prescaler (8)
ORCLK
Reload register RPS (8) (TPSAB) (TABPS) I12 (TPSAB) (TPSAB) (TABPS)
Register B
Register A
D5/INT
I13
0 1
One-sided edge detection circuit
I11 0 SQ 1 R
I10 1 0
Both edges detection circuit
I10 W13
T1UDF
W11, W10 00 01 10 11 0 W12 1 W40 (TAB1)
Timer 1 (8) Reload register R1 (8)
(T1AB) (T1AB) (T1AB) (TAB1)
T1F
Timer 1 interrupt
PWMOUT ORCLK T3UDF C/CNTR
Register B Register A
Timer 1 underflow signal (T1UDF)
PWMOUT
Port C output
Q D
T1UDF
W41
W12 W10 W11
R
T
Register B Register A
(T2HAB) T Q
PWMOD W23
Reload register R2H (8)
W20
XIN ORCLK
1 /2
0 1 W21
Reload control circuit Timer 2 (8)
(T2R2L)
W22 1
R
"H" interval expansion
T2F
0
Timer 2 interrupt
Reload register R2L (8)
(T2AB) (TAB2) (T2AB) (T2AB) (TAB2)
Register B Register A
Data is set automatically from each reload register when timer underflows (auto-reload function).
Fig. 22 Timer structure (1)
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4556 Group
XCIN
ORCLK
W33 0
Timer 3 (16)
1 W32 1 - - 4 - - - - - - - - 13 14 15 16 W31, W30 11 10 01 00
T3F
Timer 3 interrupt
Timer 3 underflow signal (T3UDF)
W42 0 STCK 1 W43
Timer LC (4)
Reload register RLC (4)
(TLCA) (TLCA)
1/2
LCD clock
Register A
INTSNC
Watchdog timer
1 - - - - - - - - - - - - - - 16 S Q
WDF1 WRST instruction RESET signal (Note) DWDT instruction + WRST instruction R S Q
WEF R D Q Watchdog reset signal
T Notes: The WEF flag is set to "1" at system reset or RAM back-up mode. Data is set automatically from each reload register when timer underflows (auto-reload function).
R
RESET signal
Fig. 23 Timer structure (2)
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4556 Group
Table 10 Timer related registers Timer control register PA PA0 Prescaler control bit 0 1 at reset : 02 Stop (state retained) Operating R/W TAW1/TW1A at power down : 02 W TPAA
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits (Note 3) Timer 1 count auto-stop circuit selection bit (Note 2) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at power down : state retained
W10
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 W20 CNTR pin output control bit PWM signal interrupt valid waveform/ return level selection bit Timer 2 control bit Timer 2 count soruce selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
CNTR pin output invalid CNTR pin output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 signal output R/W TAW3/TW3A
Timer control register W3 W33 W32 W31 Timer 3 count value selection bits W30 Timer 3 count auto-stop circuit selection bit Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
at power down : state retained
XCIN input Prescaler output (ORCLK) Stop (Initial state) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts
Timer control register W4 W43 W42 W41 W40 Timer LC control bit Timer LC count source selection bit CNTR output auto-control circuit selection bit CNTR pin input count edge selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAW4/TW4A
Stop (state retained) Operating Bit 4 (T34) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 3: Port C output is invalid when CNTR input is selected for the timer 1 count source.
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4556 Group
(1) Timer control registers
* Timer control register PA Register PA controls the count operation of prescaler. Set the contents of this register through register A with the TPAA instruction. * Timer control register W1 Register W1 controls the selection of timer 1 count auto-stop circuit, and the count operation and count source of timer 1. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. * Timer control register W2 Register W2 controls the CNTR output, the expansion of "H" interval of PWM output, and the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to transfer the contents of register W2 to register A. * Timer control register W3 Register W3 controls the count operation and count source of timer 3. Set the contents of this register through register A with the TW5A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. * Timer control register W4 Register W4 controls the operation and count source of timer LC, the selection of CNTR output auto-control circuit and the count edge of CNTR input. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to transfer the contents of register W4 to register A..
(2) Prescaler (interrupt function)
Prescaler is an 8-bit binary down counter with the prescaler reload register RPS. Data can be set simultaneously in prescaler and the reload register RPS with the TPSAB instruction. Data can be read from reload register RPS with the TABPS instruction. Stop counting and then execute the TPSAB or TABPS instruction to read or set prescaler data. Prescaler starts counting after the following process; set data in prescaler, and set the bit 0 of register PA to "1." When a value set in reload register RPS is n, prescaler divides the count source signal by n + 1 (n = 0 to 255). Count source for prescaler is the instruction clock (INSTCK). Once count is started, when prescaler underflows (the next count pulse is input after the contents of prescaler becomes "0"), new data is loaded from reload register RPS, and count continues (auto-reload function). The output signal (ORCLK) of prescaler can be used for timer 1, 2, and 3 count sources.
(3) Timer 1 (interrupt function)
Timer 1 is an 8-bit binary down counter with the timer 1 reload register (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to reload register (R1) with the TR1AB instruction. Data can be read from timer 1 with the TAB1 instruction. Stop counting and then execute the T1AB or TAB1 instruction to read or set timer 1 data. When executing the TR1AB instruction to set data to reload register R1 while timer 1 is operating, avoid a timing when timer 1 underflows. Timer 1 starts counting after the following process; set data in timer 1 set count source by bits 0 and 1 of register W1, and set the bit 2 of register W1 to "1." When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes "0"), the timer 1 interrupt request flag (T1F) is set to "1," new data is loaded from reload register R1, and count continues (auto-reload function). INT pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register I1 to "1." Also, in this time, the auto-stop function by timer 1 underflow can be performed by setting the bit 3 of register W1 to "1."
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(4) Timer 2 (interrupt function)
Timer 2 is an 8-bit binary down counter with two timer 2 reload registers (R2L, R2H). Data can be set simultaneously in timer 2 and the reload register R2L with the T2AB instruction. Data can be set in the reload register R2H with the T2HAB instruction. The contents of reload register R2L set with the T2AB instruction can be set to timer 2 again with the T2R2L instruction. Data can be read from timer 2 with the TAB2 instruction. Stop counting and then execute the T2AB or TAB2 instruction to read or set timer 2 data. When executing the T2HAB instruction to set data to reload register R2H while timer 2 is operating, avoid a timing when timer 2 underflows. Timer 2 starts counting after the following process; set data in timer 2 set count source by bit 0 of register W2, and set the bit 1 of register W2 to "1." When a value set in reload register R2L is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes "0"), the timer 2 interrupt request flag (T2F) is set to "1," new data is loaded from reload register R2L, and count continues (auto-reload function). When bit 3 of register W2 is set to "1", timer 2 reloads data from reload register R2L and R2H alternately each underflow. Timer 2 generates the PWM signal (PWMOUT) of the "L" interval set as reload register R2L, and the "H" interval set as reload register R2H. The PWM signal (PWMOUT) is output from CNTR pin. When bit 2 of register W2 is set to "1" at this time, the interval (PWM signal "H" interval) set to reload register R2H for the counter of timer 2 is extended for a half period of count source. In this case, when a value set in reload register R2H is n, timer 2 divides the count source signal by n + 1.5 (n = 1 to 255). When this function is used, set "1" or more to reload register R2H. When bit 1 of register W4 is set to "1", the PWM signal output to CNTR pin is switched to valid/invalid each timer 1 underflow. However, when timer 1 is stopped (bit 2 of register W1 is cleared to "0"), this function is canceled. Even when bit 1 of a register W2 is cleared to "0" in the "H" interval of PWM signal, timer 2 does not stop until it next timer 2 underflow. When clearing bit 1 of register W2 to "0" to stop timer 2, avoid a timing when timer 2 underflows.
(5) Timer 3 (interrupt function)
Timer 3 is a 16-bit binary down counter. Timer 3 starts counting after the following process; set count value by bits 0 and 1 of register W3, set count source by bit 3 of register W3, and set the bit 2 of register W3 to "1." Once count is started, when timer 3 underflows (the set count value is counted), the timer 3 interrupt request flag (T3F) is set to "1," and count continues. Bit 4 of timer 3 can be used as the timer LC count source for the LCD clock generating. When bit 2 of register W3 is cleared to "0", timer 3 is initialized to "FFFF16" and count is stopped. Timer 3 can be used as the counter for clock because it can be operated at clock operating mode (POF instruction execution). When timer 3 underflow occurs at clock operating mode, system returns from the power down state. When operating timer 3 during clock operating mode, set 1 cycle or more of count source to the following period; from setting bit 2 of register W3 to "1" till executing the POF instruction.
(6) Timer LC
Timer LC is a 4-bit binary down counter with the timer LC reload register (RLC). Data can be set simultaneously in timer LC and the reload register (RLC) with the TLCA instruction. Data cannot be read from timer LC. Stop counting and then execute the TLCA instruction to set timer LC data. Timer LC starts counting after the following process; set data in timer LC, select the count source with the bit 2 of register W4, and set the bit 3 of register W4 to "1." When a value set in reload register RLC is n, timer LC divides the count source signal by n + 1 (n = 0 to 15). Once count is started, when timer LC underflows (the next count pulse is input after the contents of timer LC becomes "0"), new data is loaded from reload register RLC, and count continues (auto-reload function). Timer LC underflow signal divided by 2 can be used for the LCD clock.
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(7) Timer input/output pin (C/CNTR pin)
CNTR pin is used to input the timer 1 count source and output the PWM signal generated by timer 2. When the PWM signal is output from C/CNTR pin, set "0" to the output latch of port C. The selection of CNTR output signal can be controlled by bit 3 of register W2. When the CNTR input is selected for timer 1 count source, timer 1 counts the waveform of CNTR input selected by bit 0 of register W4. Also, when the CNTR input is selected, the output of port C is invalid (high-impedance state).
(10) Count auto-stop circuit (timer 1)
Timer 1 has the count auto-stop circuit which is used to stop timer 1 automatically by the timer 1 underflow when the count start synchronous circuit is used. The count auto-stop cicuit is valid by setting the bit 3 of register W1 to "1". It is cleared by the timer 1 underflow and the count source to timer 1 is stopped. This function is valid only when the timer 1 count start synchronous circuit is selected.
(11) Precautions
Note the following for the use of timers. * Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data. * Timer count source Stop timer 1, 2, and LC counting to change its count source. * Reading the count value Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data. * Writing to the timer Stop timer 1, 2 or LC counting and then execute the data write instruction (T1AB, T2AB, TLCA) to write its data. * Writing to reload register R1, R2H When writing data to reload register R1 or reload regiser R2H while timer 1 or timer 2 is operating, avoid a timing when timer 1 or timer 2 underflows. * Timer 2 Avoid a timing when timer 2 underflows to stop timer 2 at PWM output function used. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R2H. * Timer 3 Stop timer 3 counting to change its count source. * Timer input/output pin Set the port C output latch to "0" to output the PWM signal from C/CNTR pin.
(8) Timer interrupt request flags (T1F, T2F, T3F)
Each timer interrupt request flag is set to "1" when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3). Use the interrupt control register V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to "0" when an interrupt occurs or when the next instruction is skipped with a skip instruction.
(9) Count start synchronization circuit (timer 1)
Timer 1 has the count start synchronous circuit which synchronizes the input of INT pin, and can start the timer count operation. Timer 1 count start synchronous circuit function is selected by setting the bit 0 of register I1 to "1" and the control by INT pin input can be performed. When timer 1 count start synchronous circuit is used, the count start synchronous circuit is set, the count source is input to each timer by inputting valid waveform to INT pin. The valid waveform of INT pin to set the count start synchronous circuit is the same as the external interrupt activated condition. Once set, the count start synchronous circuit is cleared by clearing the bit I10 to "0" or reset. However, when the count auto-stop circuit is selected, the count start synchronous circuit is cleared (auto-stop) at the timer 1 underflow.
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* Prescaler and Timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after Prescaler and Timer 1 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of Timer 1, Timer 1 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source
Selecting CNTR input falling edge
Timer Value
3
2
1
0
3
2
1
0
3
2
Timer Underflow signal (3) (1) Timer Start (4)
Fig. 24 Timer count start timing and count time when operation starts (Prescaler and Timer 1)
* Timer 2 and Timer LC count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source operations after count starts.
(2) Count Source
Timer Value
3
2
1
0
3
2
1
0
3
Timer Underflow Signal (3) (1) Timer Start (4)
Fig. 25 Timer count start timing and count time when operation starts (Timer 2 and Timer LC)
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q CNTR output: invalid (W23 = "0")
Timer 2 count source 0316 (R2L) (R2L) (R2L) (R2L) (R2L) 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016 0316 0216 0116 0016
Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal (output invalid)
Timer 2 start
PWM signal "L" fixed
q CNTR output: valid (W23 = "1") PWM signal "H" interval extension function: invalid (W22 = "0")
Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal 3 clock Timer 2 start PWM period 7 clock 3 clock PWM period 7 clock 0316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116
q CNTR output: valid (W23 = "1") PWM signal "H" interval extension function: valid (W22 = "1") (Note)
Timer 2 count source Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal Timer 2 start 3.5 clock PWM period 7.5 clock 3.5 clock PWM period 7.5 clock 0316 (R2L) (R2H) (R2L) (R2H) (R2L) (R2H) 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 0216
Note: At PWM signal "H" interval extension function: valid, set "0116" or more to reload register R2H.
Fig. 26 Timer 2 operation (reload register R2L: "0316", R2H: "0216")
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CNTR output auto-control circuit by timer 1 is selected.
q CNTR output: valid (W23 = "1") CNTR output auto-control circuit selected (W41 = "1") PWM signal Timer 1 underflow signal Timer 1 start CNTR output CNTR output start
q CNTR output auto-control function
PWM signal Timer 1 underflow signal Timer 1 start Register W41
Timer 1 stop
CNTR output CNTR output start CNTR output stop

When the CNTR output auto-control function is set to be invalid while the CNTR output is invalid, the CNTR output invalid state is retained. When the CNTR output auto-control function is set to be invalid while the CNTR output is valid, the CNTR output valid state is retained. When timer 1 is stopped, the CNTR output auto-control function becomes invalid. Note: When the PWM signal is output from C/CNTR pin, set the output latch of port C to "0".
Fig. 27 CNTR output auto-control function by timer 1
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qWaveform extension function of CNTR output "H" interval: Invalid (W22 = "0"), CNTR output: valid (W23 = "1"), Count source: XIN input selected (W20 = "0"), Reload register R2L: "0316" Reload register R2H: "0216"
Timer 2 count start timing
Machine cycle
Mi
Mi+1
Mi+2
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W21 Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal
TW2A instruction execution cycle (W21) 1
0316 (R2L)
0216 0116 0016 0216 0116 0016 0316 0216 0116 (R2H) (R2L)
Timer 2 count start timing
Timer 2 count stop timing
Machine cycle Mi Mi+1 Mi+2
System clock f(STCK)=f(XIN)/4 XIN input (count source selected) Register W21 Timer 2 count value (Reload register) Timer 2 underflow signal PWM signal
TW2A instruction execution cycle (W21) 0
0216 0116 0016 0216 0116 0016 0316 0216 0116 0016 (R2H) (R2L)
0216 (R2H)
(Note 1)
Timer 2 count stop timing
Notes 1: In order to stop timer 2 at CNTR output valid (W23 = "1"), avoid a timing when timer 2 underflows. If these timings overlap, a hazard may occur in a CNTR output waveform. 2: At CNTR output valid, timer 2 stops after "H" interval of PWM signal set by reload register R2H is output.
Fig. 28 Timer 2 count start/stop timing
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WATCHDOG TIMER
Watchdog timer provides a method to reset the system when a program run-away occurs. Watchdog timer consists of timer WDT(16-bit binary counter), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source from "FFFF16" after system is released from reset. After the count is started, when the timer WDT underflow occurs (after the count value of timer WDT reaches "000016," the next count pulse is input), the WDF1 flag is set to "1." If the WRST instruction is never executed until the timer WDT underflow occurs (until timer WDT counts 65534), WDF2 flag is set to "1," and the RESET pin outputs "L" level to reset the microcomputer. Execute the WRST instruction at each period of 65534 machine cycle or less by software when using watchdog timer to keep the microcomputer operating normally. When the WEF flag is set to "1" after system is released from reset, the watchdog timer function is valid. When the DWDT instruction and the WRST instruction are executed continuously, the WEF flag is cleared to "0" and the watchdog timer function is invalid. The WEF flag is set to "1" at system reset or RAM back-up mode. The WRST instruction has the skip function. When the WRST instruction is executed while the WDF1 flag is "1", the WDF1 flag is cleared to "0" and the next instruction is skipped. When the WRST instruction is executed while the WDF1 flag is "0", the next instruction is not skipped. The skip function of the WRST instruction can be used even when the watchdog timer function is invalid.
FFFF16 Value of 16-bit timer (WDT) 000016 WDF1 flag
65534 count (Note) WDF2 flag
RESET pin output
Reset released
WRST instruction executed (skip executed)
System reset
After system is released from reset (= after program is started), timer WDT starts count down. When timer WDT underflow occurs, WDF1 flag is set to "1." When the WRST instruction is executed, WDF1 flag is cleared to "0," the next instruction is skipped. When timer WDT underflow occurs while WDF1 flag is "1," WDF2 flag is set to "1" and the watchdog reset signal is output. The output transistor of RESET pin is turned "ON" by the watchdog reset signal and system reset is executed.
Note: The number of count is equal to the number of cycle because the count source of watchdog timer is the instruction clock.
Fig. 29 Watchdog timer function
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When the watchdog timer is used, clear the WDF1 flag at the period of 65534 machine cycles or less with the WRST instruction. When the watchdog timer is not used, execute the DWDT instruction and the WRST instruction continuously (refer to Figure 30). The watchdog timer is not stopped with only the DWDT instruction. The contents of WDF1 flag and timer WDT are initialized at the power down mode. When using the watchdog timer and the power down mode, initialize the WDF1 flag with the WRST instruction just before the microcomputer enters the power down state (refer to Figure 31). The watchdog timer function is valid after system is returned from the power down. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down, and stop the watchdog timer function.
WRST
***
; WDF1 flag cleared
DI DWDT WRST
***
; Watchdog timer function enabled/disabled ; WEF and WDF1 flags cleared
Fig. 30 Program example to start/stop watchdog timer
WRST ; WDF1 flag cleared NOP DI ; Interrupt disabled EPOF ; POF instruction enabled POF Oscillation stop
Fig. 31 Program example to enter the mode when using the watchdog timer
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***
***
***
4556 Group
LCD FUNCTION
The 4556 Group has an LCD (Liquid Crystal Display) controller/ driver. When the proper voltage is applied to LCD power supply input pins (VLC1-VLC3) and data are set in timer control register (W4), timer LC, LCD control registers (L1, L2, L3, C1, C2), and LCD RAM, the LCD controller/driver automatically reads the display data and controls the LCD display by setting duty and bias. 4 common signal output pins and 23 segment signal output pins can be used to drive the LCD. By using these pins, up to 92 segments (when 1/4 duty and 1/3 bias are selected) can be controlled to display. The LCD power input pins (VLC1-VLC3) are also used as pins SEG0-SEG2. When SEG0-SEG2 are selected, the internal power (VDD) is used for the LCD power.
(2) LCD clock control
The LCD clock is determined by the timer LC count source selection bit (W42), timer LC control bit (W43), and timer LC. Accordingly, the frequency (F) of the LCD clock is obtained by the following formula. Numbers ( to ) shown below the formula correspond to numbers in Figure 32, respectively. * When using the prescaler output (ORCLK) as timer LC count source (W42="1") F = ORCLK 1 LC + 1 1 2
(1) Duty and bias
There are 3 combinations of duty and bias for displaying data on the LCD. Use bits 0 and 1 of LCD control register (L1) to select the proper display method for the LCD panel being used. * 1/2 duty, 1/2 bias * 1/3 duty, 1/3 bias * 1/4 duty, 1/3 bias Table 11 Duty and maximum number of displayed pixels Duty 1/2 1/3 1/4 Maximum number of displayed pixels Used COM pins 46 segments COM0, COM1 (Note) 69 segments COM0-COM2 (Note) 92 segments COM0-COM3
* When using the bit 4 of timer 3 as timer LC count source (W42="0") F = T34 [LC: 0 to 15] The frame frequency and frame period for each display method can be obtained by the following formula: Frame frequency = F n n F (Hz) 1 LC + 1 1 2
Frame period =
(s) F: LCD clock frequency 1/n: Duty
Note: Leave unused COM pins open.
(Note) W43 W42 T34 STCK 0 1 Reload register RLC ( TLCA ) ( TLCA ) (4 ) 0 1 Timer LC (4 ) 1/2 LCD clock
Register A Note: Count source is stopped by setting "0" to this bit.
Fig. 32 LCD clock control circuit structure
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SEG0/VLC3 COM3 COM1 COM2 COM0
SEG2/VLC1 SEG3 to SEG17 to SEG10 SEG28
SEG1 /VLC2
r r r r
SEG0 to SEG2 output
.........
Multiplexer
r r
Control signal
Common driver
Bias control
Segment driver
...
Segment driver
Selector
... Selector ...
RAM
Decoder
1/2,1/3,1/4 counter LCD clock (from timer block)
RAM
LCD ON/ OFF control L13 L12 L11 L10 L23 L22 L21 L20
Register A
Fig. 33 LCD controller/driver
(3) LCD RAM
RAM contains areas corresponding to the liquid crystal display. When "1" is written to this LCD RAM, the display pixel corresponding to the bit is automatically displayed.
(4) LCD drive waveform
When "1" is written to a bit in the LCD RAM data, the voltage difference between common pin and segment pin which correspond to the bit automatically becomes lVLC3l and the display pixel at the cross section turns on. When returning from reset, and in the RAM back-up mode, a display pixel turns off because every segment output pin and common output pin becomes VLC3 level.
Z X Y 8 9 10 11 12 13 14 15 COM
Bits
1 0 3 2 1 0 3 2 1 1 0 3 2 2 1 0 3 2 3 1 0
SEG0 SEG0 SEG0 SEG0 SEG8 SEG8 SEG8 SEG8 SEG24 SEG24 SEG24 SEG24 SEG1 SEG1 SEG1 SEG1 SEG9 SEG9 SEG9 SEG9 SEG17 SEG17 SEG17 SEG17 SEG25 SEG25 SEG25 SEG25 SEG2 SEG2 SEG2 SEG2 SEG10 SEG10 SEG10 SEG10 SEG18 SEG18 SEG18 SEG18 SEG26 SEG26 SEG26 SEG26 SEG3 SEG3 SEG3 SEG3 SEG4 SEG4 SEG4 SEG4 SEG5 SEG5 SEG5 SEG5 SEG19 SEG20 SEG21 SEG22 SEG19 SEG19 SEG20 SEG20 SEG21 SEG21 SEG22 SEG22 SEG19 SEG27 SEG27 SEG27 SEG27 SEG20 SEG28 SEG28 SEG28 SEG28 SEG21 SEG22
SEG6 SEG6 SEG6 SEG6 SEG7 SEG7 SEG7 SEG7 SEG23 SEG23 SEG23 SEG23 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0
Note: The area marked "
" is not the LCD display RAM.
Fig. 34 LCD RAM map
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Table 12 LCD control registers (1) LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1 L11 L10 0 0 0 1 1 0 1 1 at reset : 00002 2r 3, 2r 2 r 3, r 2 Stop Operating Duty Not available 1/2 1/3 1/4 1/2 1/3 1/3 W TL2A Bias at power down : state retained R/W TAL1/TL1A
LCD control register L2 L23 L22 L21 L20 SEG0/VLC3 pin function switch bit (Note 3) SEG1/VLC2 pin function switch bit (Note 4) SEG2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1
at reset : 00002 SEG0
at power down : state retained
VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid
LCD control register L3 L33 L32 L31 L30 P23/SEG20 pin function switch bit P22/SEG19 pin function switch bit P21/SEG18 pin function switch bit P20/SEG17 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG20 P23 SEG19 P22 SEG18 P21 SEG17 P20
at power down : state retained
W TL3A
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
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Table 12 LCD control registers (2) LCD control register C1 C13 C12 C11 C10 P03/SEG24 pin function switch bit P02/SEG23 pin function switch bit P01/SEG22 pin function switch bit P00/SEG21 pin function switch bit 0 1 0 1 0 1 0 1 at reset : 11112 SEG24 P03 SEG23 P02 SEG22 P01 SEG21 P00 W TC2A at power down : state retained W TC1A
LCD control register C2 C23 C22 C21 C20 P13/SEG28 pin function switch bit P12/SEG27 pin function switch bit P11/SEG26 pin function switch bit P10/SEG25 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG28 P13 SEG27 P12 SEG26 P11 SEG25 P10
at power down : state retained
Note: "R" represents read enabled, and "W" represents write enabled.
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1/2 Duty, 1/2 Bias: When writing (XX10)2 to address M (1, 2, 9) in RAM. 1 flame (2/F) M (1, 2, 9) COM0 COM1 1/F COM1
Voltage level
0 (bit 0) 1 X X (bit 3)
COM0
VLC3 VLC1=VLC2 VSS
SEG17
SEG17
COM1 SEG17 COM0 SEG17
VLC3 VLC1=VLC2 VSS
ON 1/3 Duty, 1/3 Bias: When writing (X101)2 to address M (1, 2, 9) in RAM.
OFF
1 flame (3/F) M (1, 2, 9) COM0 COM1 COM2 1/F COM2
Voltage level
1 (bit 0) 0 1 X (bit 3)
COM1
VLC3 VLC2 VLC1 VSS
SEG17 COM0 VLC3 VLC2 VLC1 VSS
SEG17
COM2 SEG17 COM1 SEG17 COM0 SEG17
ON
OFF
ON
1/4 Duty, 1/3 Bias: When writing (1010)2 to address M (1, 2, 9) in RAM. 1 flame (4/F) M (1, 2, 9) COM0 COM1 COM2 COM3 SEG17 COM1 1/F COM3
Voltage level
0 (bit 0) 1 0 1 (bit 3)
COM2
VLC3 VLC2 VLC1 VSS
COM0 VLC3 VLC2 VLC1 VSS
F : LCD clock frequency
SEG17
COM3 SEG17 COM2 SEG17 COM1 SEG17 COM0 SEG17
X: Set an arbitrary value. (These bits are not related to set the drive waveform at each duty.)
ON
OFF
ON
OFF
Fig. 35 LCD controller/driver structure
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(5) LCD power supply circuit
Select the LCD power supply circuit suitable for the using LCD panel. The LCD power supply circuit is fixed by the followings; * The internal dividing resistor is controlled by bit 0 of register L2. * The internal dividing resistor is selected by bit 3 of register L1. * The bias condition is selected by bits 0 and 1 of register L1. qInternal dividing resistor The 4556 Group has the internal dividing resistor for LCD power supply. When bit 0 of register L2 is set to "0", the internal dividing resistor is valid. However, when the LCD is turned off by setting bit 2 of register L1 to "0", the internal dividing resistor is turned off. The same six resistor (r) is prepared for the internal dividing resistor. According to the setting value of bit 3 of register L1 and using bias condition, the resistor is prepared as follows; * L13 = "0", 1/3 bias used: 2r 3 = 6r * L13 = "0", 1/2 bias used: 2r 2 = 4r * L13 = "1", 1/3 bias used: r 3 = 3r * L13 = "1", 1/2 bias used: r 2 = 2r
qVLC3/SEG0 pin The selection of VLC3/SEG0 pin function is controlled with the bit 3 of register L2. When the VLC3 pin function is selected, apply voltage of VLC3 < VDD to the pin externally. When the SEG0 pin function is selected, VLC3 is connected to VDD internally. q VLC2/SEG1, VLC1/SEG2 pin The selection of VLC2/SEG1 pin function is controlled with the bit 2 of register L2. The selection of VLC1/SEG2 pin function is controlled with the bit 1 of register L2. When the VLC2 pin and VLC1 pin functions are selected and the internal dividing resistor is not used, apply voltage of 0VLC3
SEG0
VLC3
VLC3
VLC2
SEG1
VLC2
SEG1
VLC1 SEG2
VLC1 SEG2
a) Register L2=(0000)2
b) Register L2=(1000)2
VLC3
VLC3
VLC3
VLC3
VLC2 VLC2 VLC2 VLC2
VLC1 VLC1 VLC1 VLC1
c) Register L2=(1110)2
d) Register L2=(1111)2
Fig. 36 LCD power supply circuit example (1/3 bias condition selected)
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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4556 Group
RESET FUNCTION
System reset is performed by applying "L" level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when "H" level is applied to RESET pin, software starts from address 0 in page 0.
f(RING)
RESET On-chip oscillator (internal oscillator)
is counted 1376 times.
Program starts (address 0 in page 0)
Note: The number of clock cycles depends on the internal state of the microcomputer when reset is performed.
Fig. 37 Reset release timing
Reset input
=
On-chip oscillator (internal oscillator) is
1 machine cycle or more
counted 1376 times.
0.85VDD RESET 0.3VDD
Program starts (address 0 in page 0)
(Note)
Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 38 RESET pin input waveform and reset operation
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4556 Group
(1) Power-on reset
Reset can be automatically performed at power on (power-on reset) by the built-in power-on reset circuit. When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 s or less.
If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
100 s or less
VDD (Note 3)
Pull-up transistor
(Note 1) (Note 2)
Power-on reset circuit output
RESET pin
(Note 1)
Internal reset signal
Power-on reset circuit Voltage drop detection circuit (only for H version) Watchdog reset signal WEF SRST instruction
Internal reset signal
Reset state Power-on Reset released
This symbol represents a parasitic diode. Notes 1: 2: Applied potential to RESET pin must be VDD or less. 3: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions.
Fig. 39 Structure of reset pin and its peripherals,, and power-on reset operation Table 13 Port state at reset Name D0-D4 D5/INT XCIN/D6, XCOUT/D7 P00/SEG21-P03/SEG24 P10/SEG25-P13/SEG28 P20/SEG17-P23/SEG20 SEG0/VLC3-SEG2/VLC1 SEG3-SEG10 COM0-COM3 C/CNTR D0-D4 D5 XCIN, XCOUT P00-P03 P10-P13 P20-P23 SEG0-SEG2 SEG3-SEG10 COM0-COM3 C Function High-impedance (Notes 1, 2) High-impedance (Notes 1, 2) Sub-clock input High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) High-impedance (Notes 1, 2, 3) VLC3 (VDD) level VLC3 (VDD) level VLC3 (VDD) level "L" (VSS) level State
Notes 1: Output latch is set to "1." 2: Output structure is N-channel open-drain. 3: Pull-up transistor is turned OFF.
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4556 Group
(2) Internal state at reset
Figure 40 shows internal state at reset (they are the same after system is released from reset). The contents of timers, registers, flags and RAM except shown in Figure 40 are undefined, so set the initial value to them.
* Program counter (PC) .......................................................................................................... 0 00000 Address 0 in page 0 is set to program counter. * Interrupt enable flag (INTE) .................................................................................................. 0 * Power down flag (P) ............................................................................................................. 0 * External 0 interrupt request flag (EXF0) .............................................................................. 0 000 * Interrupt control register V1 .................................................................................................. 0 * Interrupt control register V2 .................................................................................................. 0 000 000 * Interrupt control register I1 ................................................................................................... 0 * Timer 1 interrupt request flag (T1F) ..................................................................................... 0 * Timer 2 interrupt request flag (T2F) ..................................................................................... 0 * Timer 3 interrupt request flag (T3F) ..................................................................................... 0 * Watchdog timer flags (WDF1, WDF2) .................................................................................. 0 * Watchdog timer enable flag (WEF) ...................................................................................... 1 * Timer control register PA ...................................................................................................... 0 000 * Timer control register W1 ..................................................................................................... 0 * Timer control register W2 ..................................................................................................... 0 000 000 * Timer control register W3 ..................................................................................................... 0 000 * Timer control register W4 ..................................................................................................... 0 * Clock control register MR ..................................................................................................... 0 110 00 * Clock control register RG ..................................................................................................... 0 * LCD control register L1 ........................................................................................................ 0 000 * LCD control register L2 ........................................................................................................ 0 000 111 * LCD control register L3 ........................................................................................................ 1 * LCD control register C1 ........................................................................................................ 1 111 * LCD control register C2 ........................................................................................................ 1 111 000 * Key-on wakeup control register K0 ...................................................................................... 0 * Key-on wakeup control register K1 ...................................................................................... 0 000 * Key-on wakeup control register K2 ...................................................................................... 0 000 000 * Pull-up control register PU0 ................................................................................................. 0 * Pull-up control register PU1 ................................................................................................. 0 000 * Port output structure control register FR0 ........................................................................... 0 000 000 * Port output structure control register FR1 ........................................................................... 0 * Port output structure control register FR2 ........................................................................... 0 000 * Carry flag (CY) ...................................................................................................................... 0 * High-order bit reference enable flag (UPTF) ....................................................................... 0 * Register A ............................................................................................................................. 0 000 * Register B ............................................................................................................................. 0 000 * Register D ............................................................................................................................. * Register E ............................................................................................................................. * Register X ............................................................................................................................. 0 000 000 * Register Y ............................................................................................................................. 0 * Register Z ............................................................................................................................. * Stack pointer (SP) ................................................................................................................ 1 11 * Operation source clock .......................................................... On-chip oscillator (operating) * Ceramic resonator circuit ..................................................................................... Operating * RC oscillation circuit ...................................................................................................... Stop * Quartz-crystal oscillator ........................................................................................ Operating
0
0
0
0
0
0
0
0
(Interrupt disabled)
(Interrupt disabled) (Interrupt disabled)
(Prescaler stopped) (Timer 1 stopped) (Timer 2 stopped) (Timer 3 stopped) (Timer LC stopped)
"" represents undefined. Fig. 40 Internal state at reset
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4556 Group
VOLTAGE DROP DETECTION CIRCUIT (only for H version)
The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value.
(1) SVDE instruction When the SVDE instruction is executed, the voltage drop deteciton circuit is valid even after system enters into the power down mode. The SVDE instruction can be executed only once. In order to release the execution of the SVDE instruction, the system reset is required.
S Q R EPOF instruction +POF instruction EPOF instruction +POF2 instruction Internal reset signal T3F flag Key-on wakeup signal SVDE instruction Internal reset signal
Q
S R
- VRST +
Voltage drop detection circuit Reset signal
Voltage drop detection circuit
Fig. 41 Voltage drop detection reset circuit
VRST (reset release voltage) VRST -(reset occurrence voltage)
+
VDD
Voltage drop detection circuit Reset signal Microcomputer starts operation after on-chip oscillator (internal oscillator) clock is counted 1376 times. RESET pin
Note: Detection voltage hysteresis of voltage drop detection circuit is 0.1 V (Typ).
Fig. 42 Voltage drop detection circuit operation waveform (2) Note on voltage drop detection circuit The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 43); supply voltage does not fall below to VRST-, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that.
VDD Recommended operatng condition min.value + VRST - VRST
No reset Program failure may occur.
VDD Recommended operatng condition min.value + VRST - VRST Reset
Normal operation
Fig. 43 VDD and VRST-
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4556 Group
POWER DOWN FUNCTION
The 4556 Group has 2-type power down functions. System enters into each power down state by executing the following instructions. * Clock operating mode ...................... EPOF and POF instructions * RAM back-up mode ....................... EPOF and POF2 instructions When the EPOF instruction is not executed before the POF or POF2 instruction is executed, these instructions are equivalent to the NOP instruction.
Table 15 Functions and states retained at power down mode Power down mode Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Interrupt control registers V1, V2 Interrupt control register I1 Selected oscillation circuit Clock control register MR, RG Timer 1 to timer 2 functions Timer 3 function Timer LC function Watchdog timer function Timer control registers PA Timer control registers W1 to W4 LCD display function LCD control registers L1 to L3, C1, C2 Voltage drop detection circuit Port level Pull-up control registers PU0, PU1 Key-on wakeup control registers K0 to K2 Port output structure control registers FR0 to FR2 External interrupt request flag (EXF0) Timer interrupt request flags (T1F, T2F) Timer interrupt request flag (T3F) Interrupt enable flag (INTE) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) (Note 3) O (Note 3) (Note 3)
Clock operating RAM back-up
O O O O (Note 3) O O O O O (Note 6) (Note 7) O O O
O O O O (Note 3) (Note 3) (Note 3) O (Note 5) O (Note 6) (Note 7) O O O
(1) Clock operating mode
The following functions and states are retained. * RAM * Reset circuit * XCIN-XCOUT oscillation * LCD display * Timer 3
(Note 4) (Note 4)
(2) RAM back-up mode
The following functions and states are retained. * RAM * Reset circuit
(3) Warm start condition
The system returns from the power down state when; * External wakeup signal is input * Timer 3 underflow occurs in the power down mode. In either case, the CPU starts executing the software from address 0 in page 0. In this case, the P flag is "1."
(Note 4) (Note 4) (Note 4) (Note 4)
(4) Cold start condition
The CPU starts executing the software from address 0 in page 0 when; * reset pulse is input to RESET pin, * reset by watchdog timer is performed, or * reset by the voltage drop detection circuit is performed. In this case, the P flag is "0."
(5) Identification of the start condition
Warm start or cold start can be identified by examining the state of the power down flag (P) with the SNZP instruction. The warm start condition from the clock operating mode can be identified by examining the state of T3F flag.
Notes 1:"O" represents that the function can be retained, and "" represents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to "7" at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then go into the power down state. 5: LCD is turned off. 6: When the SVDE instruction is executed, this function is valid at power down. 7: In the RAM back-up mode, C/CNTR pin outputs "L" level. However, when the CNTR input is selected (W11, W10="11"), C/ CNTR pin is in an input enabled state (output = high-impedance). Other ports retain their respective output levels.
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4556 Group
(6) Return signal
An external wakeup signal or timer 3 interrupt request flag (T3F) is used to return from the clock operating mode. An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 16 shows the return condition for each return source.
(7) Control registers
* Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K1 Register K1 controls the return condition and the selection of valid waveform/level of port P1. Set the contents of this register through register A with the TK1A instruction. In addition, the TAK1 instruction can be used to transfer the contents of register K0 to register A. * Key-on wakeup control register K2 Register K2 controls the INT pin key-on wakeup function and the selection of return codition. Set the contents of this register through register A with the TK2A instruction. In addition, the TAK2 instruction can be used to transfer the contents of register K2 to register A. Table 16 Return source and return condition Return source Return condition Ports P00-P03 Return by an external falling edge ("H""L"). Ports P10-P13 Return by an external "H" level or "L" level input, or rising edge ("L""H") or falling edge ("H""L"). Return by an external "L" level input. INT pin Return by an external "H" level or "L" level input, or rising edge ("L""H") or falling edge ("H""L"). When the return level is input, the interrupt request flag (EXF0) is not set.
* Pull-up control register PU0 Register PU0 controls the ON/OFF of the port P0 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. * Pull-up control register PU1 Register PU1 controls the ON/OFF of the port P1 pull-up transistor. Set the contents of this register through register A with the TPU1A instruction. In addition, the TAPU1 instruction can be used to transfer the contents of register PU1 to register A. * External interrupt control register I1 Register I1 controls the valid waveform of the external 0 interrupt, the input control of INT pin and the return input level. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A.
Remarks The key-on wakeup function can be selected by two port unit. The key-on wakeup function can be selected by two port unit. Select the return level ("L" level or "H" level) and return condition (return by level or edge) with register K1 according to the external state before going into the power down state. Select the return level ("L" level or "H" level) with register I1 and return condition (return by level or edge) with register K2 according to the external state before going into the power down state.
Timer 3 interrupt Return by timer 3 underflow or by request flag (T3F) setting T3F to "1". It can be used in the clock operating mode.
External wakeup signal
Clear T3F with the SNZT3 instruction before system enters into the power down state. When system enters into the power down state while T3F is "1", system returns from the state immediately because it is recognized as return condition.
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4556 Group
High-speed mode E
Clock operating mode CRCK instruction no execution POF instruction execution
B
Operation state * Operation source clock: f(XIN) * Oscillation circuit: Ceramic resonator CRCK instruction execution
POF2 instruction execution
F
Power down mode
Key-on wakeup (Stabilizing time c )
Key-on wakeup (Stabilizing time c )
POF instruction execution
C
Operation state * Operation source clock: f(XIN) * Oscillation circuit: RC oscillation
POF2 instruction execution
Key-on wakeup (Stabilizing time d )
Key-on wakeup (Stabilizing time d )
MR1, MR010
Internal mode
POF instruction execution
Reset
A
Operation state * Operation source clock: f(RING) * Oscillation circuit: On-chip oscillator MR1, MR000
MR1, MR001
MR1, MR001
MR1, MR000
(Stabilizing time a )
POF2 instruction execution Key-on wakeup (Stabilizing time b )
Key-on wakeup (Stabilizing time b )
MR1, MR010
Low-speed mode
POF instruction execution f(RING): stop f(XIN): stop f(XCIN): operating
Stabilizing time Stabilizing time Stabilizing time Stabilizing time Stabilizing time
D
Operation state * Operation source clock: f(XCIN) * Oscillation circuit: Quartz-crystal oscillation
POF2 instruction execution Key-on wakeup (Stabilizing time e ) f(RING): stop f(XIN): stop f(XCIN): stop
Key-on wakeup (Stabilizing time e )
a : Microcomputer starts its operation after counting the f(RING) to 1376 times. b : Microcomputer starts its operation after counting the f(RING) to (system clock division ratio 15) times. c : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio 171) times. d : Microcomputer starts its operation after counting the f(XIN) to (system clock division ratio 15) times. e : Microcomputer starts its operation after counting the f(XCIN) to (system clock division ratio 171) times.
Notes 1: Selection of the system clock by the clock control registers MR and RG is state retained at power down. The waiting time to stabilize oscillation at return can be adjustment by setting the clock control registers MR and RG before transition to the power down state. 2: Continuous execution of the EPOF instruction and the POF instruction is required to go into the clock operating state. 3: Continuous execution of the EPOF instruction and the POF2 instruction is required to go into the RAM back-up state. 4: The state after system is released from reset; * A ceramic oscillation is selected as the main clock (f(XIN)). * Main clock (f(XIN)) and Suc-clock (f(XCIN)) are valid. 5: When the RC oscillation circuit is used, executing the CRCK instruction is required. If the CRCK instruction is not executed, the ceramic oscillation is selected as the main clock f(XIN). 6: When the unoperating clock is selected as the system clock, turn it on by the clock control register RG, and generate the wait time until the oscillation is stabilized, and then, switch the system clock.
Fig. 44 State transition
POF or EPOF instruction + POF2 instruction Reset input
Power down flag P S Q
Program start Yes Warm start
R
P = "1" ? No Cold start
POF or q Set source * * * * * * * EPOF instruction + POF2 instruction q Clear source * * * * * * Reset input
Yes
T3F = "1" ? No
Return from timer 3 underflow
Return from external wakeup signal
Fig. 45 Set source and clear source of the P flag
Fig. 46 Start condition identified example using the SNZP instruction
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4556 Group
Table 17 Key-on wakeup control register, pull-up control register and interrupt control register Key-on wakeup control register K0 K03 K02 K01 K00 Port P12, P13 key-on wakeup control bit (Note 3) Port P10, P11 key-on wakeup control bit (Note 2) Port P02, P03 key-on wakeup control bit Port P00, P01 key-on wakeup control bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : state retained R/W TAK0/ TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/ TK1A
Key-on wakeup control register K1 K13 K12 K11 K10 Ports P12, P13 return condition selection bit (Note 3) Ports P12, P13 valid waveform/level selection bit (Note 3) Ports P10, P11 return condition selection bit (Note 2) Ports P10, P11 valid waveform/level selection bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002 Returned by edge Returned by level
at power down : state retained
Falling waveform/"L" level Rising waveform/"H" level Returned by edge Returned by level Falling waveform/"L" level Rising waveform/"H" level R/W TAK2/ TK2A
Key-on wakeup control register K2 K23 K22 K21 K20 Not used Not used INT pin return condition selection bit INT pin key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: To be invalid (K02 = "0") key-on wakeup of ports P10 and P11, set the registers K10 and K11 to "0". 3: To be invalid (K03 = "0") key-on wakeup of ports P12 and P13, set the registers K12 and K13 to "0".
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4556 Group
Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU0/ TPU0A
Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU1/ TPU1A
Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAI1/TI1A
INT pin input disabled INT pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 2)
I11 I10
INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set.
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4556 Group
CLOCK CONTROL
The clock control circuit consists of the following circuits. * On-chip oscillator (internal oscillator) * Ceramic resonator * RC oscillation circuit * Quartz-crystal oscillation circuit * Multi-plexer (clock selection circuit) * Frequency divider * Internal clock generating circuit
The system clock and the instruction clock are generated as the source clock for operation by these circuits. Figure 47 shows the structure of the clock control circuit. The 4556 Group operates by the on-chip oscillator clock (f(RING)) which is the internal oscillator after system is released from reset. Also, the ceramic resonator or the RC oscillation can be used for the main clock (f(XIN)) of the 4556 Group. The quartz-crystal oscillator can be used for sub-clock (f(XCIN)).
Division circuit Divided by 8 MR1, MR0 00 01 10
MR3, MR2 11 10
System clock (STCK) Internal clock generating circuit (divided by 3)
Divided by 4 Divided by 2
01 00
On-chip oscillator (internal oscillator)
Instruction clock (INSTCK)
RG0 XIN XOUT
Ceramic resonance
Multiplexer RG1
QS QR
CRCK instruction
RC oscillation
XCIN XCOUT
QS Quartz-crystal oscillation R QS RG2 R
Internal reset signal T3F signal Key-on wakeup signal EPOF instruction + POF instruction
EPOF instruction + POF2 instruction
Fig. 47 Clock control circuit structure
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4556 Group
(1) On-chip oscillator operation
After system is released from reset, the MCU starts operation by the clock output from the on-chip oscillator which is the internal oscillator. The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products.
Main clock (f(XIN)) * Ceramic oscillation circuit valid * RC oscillation circuit invalid
Reset
CRCK
(2) Main clock generating circuit (f(XIN))
When the MCU operates by the ceramic resonator or the RC oscillator as the main clock (f(XIN)). After system is released from reset, the ceramic oscillation is valid for main clock. The ceramic oscillation is invalid and the RC oscillation circuit is valid with the CRCK instruction. The CRCK instruction can be executed only once. Execute the CRCK instruction in the initial setting routine (executing it in address 0 in page 0 is recommended). When the main clock (f(XIN)) is not used, connect XIN pin to VSS and leave XOUT pin open, and do not execute the CRCK instruction (Figure 49).
* Ceramic oscillation circuit invalid * RC oscillation circuit valid
Fig. 48 Switch to ceramic oscillation/RC oscillation
M34556
* Do not use the CRCK instruction in program.
XOUT
XIN
(3) Ceramic resonator
When the ceramic resonator is used as the main clock (f(XIN)), connect the ceramic resonator and the external circuit to pins XIN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT (Figure 50). Do not execute the CRCK instruction in program.
Fig. 49 Handling of XIN and XOUT when operating on-chip oscillator
M34556
* Do not execute the CRCK instruction in program.
XOUT
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. Rd (A feedback resistor is built-in.) Use the resonator manufacturer's recommended value COUT because constants such as capacitance depend on the resonator.
XIN
(4) RC oscillation
When the RC oscillation is used as the main clock (f(XIN)), connect the XIN pin to the external circuit of resistor R and the capacitor C at the shortest distance and leave XOUT pin open. Then, execute the CRCK instruction (Figure 51). The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
CIN
Fig. 50 Ceramic resonator external circuit
M34556
R C
XIN
XOUT
* Execute the CRCK instruction in program.
Fig. 51 External RC circuit
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4556 Group
(5) External clock
When the external clock signal is used as the main clock (f(XIN)), connect the XIN pin to the clock source and leave XOUT pin open. (Figure 52). Do not execute the CRCK instruction. Be careful that the maximum value of the oscillation frequency when using the external clock differs from the value when using the ceramic resonator (refer to the recommended operating condition). Also, note that the power down mode (POF and POF2 instructions) cannot be used when using the external clock.
M34556
not use * Doprogram.the CRCK instruction in
XOUT VDD VSS
XIN
External oscillation circuit
Fig. 52 External clock input circuit
(6) Sub-clock generating circuit f(XCIN)
Sub-clock signal f(XCIN) is obtained by externally connecting a quartz-crystal oscillator. Connect this external circuit and a quartzcrystal oscillator to pins XCIN and XCOUT at the shortest distance. A feedback resistor is built in between pins XCIN and XCOUT (Figure 53). XCIN pin and XCOUT pin are also used as ports D6 and D7, respectively. The sub-clock oscillation circuit is invalid and the function of ports D6 and D7 are valid by setting bit 2 of register RG to "1". When sub-clock, ports D6 and D7 are not used, connect XCIN/D6 to VSS and leave XCOUT/D7 open.
M34556
XCIN
XCOUT
CIN
Note: Externally connect a damping resistor Rd depending on the oscillation frequency. (A feedback resistor is built-in.) Use the quartz-crystal manuRd facturer's recommended value because constants such as capacitance depend on the COUT resonator.
(7) Clock control register MR
Register MR controls system clock. Set the contents of this register through register A with the TMRA instruction. In addition, the TAMR instruction can be used to transfer the contents of register MR to register A.
Fig. 53 External quartz-crystal circuit
ROM ORDERING METHOD
1.Mask ROM Order Confirmation Form* 2.Mark Specification Form* 3.Data to be written to ROM...one floppy disk. * For the mask ROM confirmation and the mark specifications, refer to the "Renesas Technology Corp." Homepage (http://www.renesas.com/homepage.jsp).
(8) Clock control register RG
Register RG controls the start/stop of each oscillation circuit. Set the contents of this register through register A with the TRGA instruction. Table 18 Clock control registers Clock control register MR MR3 Operation mode selection bits MR2
at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 MR1 MR0 0 0 0 1 1 0 1 1
at power down : state retained Operation mode
R/W TAMR/ TMRA
Through mode Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode System clock f(RING) f(XIN) f(XCIN) Not available (Note 2) W TRGA Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected Main clock (f(XIN)) oscillation available Main clock (f(XIN)) oscillation stop On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) oscillation stop at power down : state retained
MR3 System clock selection bits (Note 3) MR2
Clock control register RG RG2 RG1 RG0 Sub-clock (f(XCIN)) control bit (Note 2) Main-clock (f(XIN)) control bit (Note 2) On-chip oscillator (f(RING)) control bit (Note 2) 0 1 0 1 0 1
at reset : 0002
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "11" cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
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NOTES ON NOISE
Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 1. Shortest wiring length (1) Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the VSS pin with the shortest possible wiring. In order to reset a microcomputer correctly, 1 machine cycle or more of the width of a pulse input into the RESET pin is required. If noise having a shorter pulse width than this is input to the RESET input pin, the reset is released before the internal state of the microcomputer is completely initialized. This may cause a program runaway.
(2) Wiring for clock input/output pins * Make the length of wiring which is connected to clock I/O pins as short as possible. * Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. * Separate the VSS pattern only for oscillation from other VSS patterns. If noise enters clock I/O pins, clock waveforms may be deformed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the VSS level of a microcomputer and the VSS level of an oscillator, the correct clock will not be input in the microcomputer.
Noise
Noise
N.G.
XIN XOUT VSS
XIN XOUT VSS
O.K.
Reset circuit VSS
N.G.
RESET VSS
Fig. 55 Wiring for clock I/O pins
Reset circuit VSS
RESET VSS
O.K.
Fig. 54 Wiring for the RESET pin
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(3) Wiring to CNVSS pin Connect CNVSS pin to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. In order to improve the noise reduction, to connect a 5 k resistor serially to the CNVSS pin - GND line may be valid. As well as the above-mentioned, in this case, connect to a GND pattern at the shortest distance. The GND pattern is required to be as close as possible to the GND supplied to VSS. The CNVSS pin of the One Time PROM is the power source input pin for the built-in One Time PROM. When programming in the built-in One Time PROM, the impedance of the CNVSS pin is low to allow the electric current for writing flow into the One Time PROM. Because of this, noise can enter easily. If noise enters the CNVSS pin, abnormal instruction codes or data are read from the built-in One Time PROM, which may cause a program runaway.
2. Connection of bypass capacitor across VSS line and VDD line Connect an approximately 0.1 F bypass capacitor across the VSS line and the VDD line as follows: * Connect a bypass capacitor across the VSS pin and the VDD pin at equal length. * Connect a bypass capacitor across the VSS pin and the VDD pin with the shortest possible wiring. * Use lines with a larger diameter than other signal lines for VSS line and VDD line. * Connect the power source wiring via a bypass capacitor to the VSS pin and the VDD pin.
VDD
VDD
(Note)
The shortest
VSS
VSS
CNVSS About 5k VSS
(Note)
N.G.
O.K.
The shortest
Fig. 57 Bypass capacitor across the VSS line and the VDD line
Note: This indicates pin.
Fig. 56 Wiring for the CNVSS pin of the One Time PROM
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3. Oscillator concerns Take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. (1) Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the tolerance of current value flows. In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise occurs because of mutual inductance. (2) Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway.
(3) Oscillator protection using Vss pattern As for a two-sided printed circuit board, print a Vss pattern on the underside (soldering side) of the position (on the component side) where an oscillator is mounted. Connect the Vss pattern to the microcomputer Vss pin with the shortest possible wiring. Besides, separate this Vss pattern from other Vss patterns.
An example of VSS patterns on the underside of a printed circuit board Oscillator wiring pattern example
XIN XOUT VSS
Separate the VSS line for oscillation from other VSS lines
Fig. 60 Vss pattern on the underside of an oscillator
Microcomputer Mutual inductance M Large current GND
Fig. 58 Wiring for a large current signal line
XIN XOUT VSS
N.G.
Do not cross
CNTR XIN XOUT VSS
Fig. 59 Wiring to a signal line where potential levels change frequently
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4. Setup for I/O ports Setup I/O ports using hardware and software as follows: * Connect a resistor of 100 or more to an I/O port in series. * As for an input port, read data several times by a program for checking whether input levels are equal or not. * As for an output port or an I/O port, since the output data may reverse because of noise, rewrite data to its port latch at fixed periods. * Rewrite data to pull-up control registers at fixed periods. 5. Providing of watchdog timer function by software If a microcomputer runs away because of noise or others, it can be detected by a software watchdog timer and the microcomputer can be reset to normal operation. This is equal to or more effective than program runaway detection by a hardware watchdog timer. The following shows an example of a watchdog timer provided by software. In the following example, to reset a microcomputer to normal operation, the main routine detects errors of the interrupt processing routine and the interrupt processing routine detects errors of the main routine. This example assumes that interrupt processing is repeated multiple times in a single main routine processing.
* Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1 (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin. * Watches the operation of the interrupt processing routine by comparing the SWDT contents with counts of interrupt processing after the initial value N has been set. * Detects that the interrupt processing routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents do not change after interrupt processing. * Decrements the SWDT contents by 1 at each interrupt processing. * Determines that the main routine operates normally when the SWDT contents are reset to the initial value N at almost fixed cycles (at the fixed interrupt processing count). * Detects that the main routine has failed and determines to branch to the program initialization routine for recovery processing in the following case: If the SWDT contents are not initialized to the initial value N but continued to decrement and if they reach 0 or less.
Main routine (SWDT) N EI Main processing N (SWDT) = N? N
Interrupt processing routine (SWDT) (SWDT)--1 Interrupt processing >0 R TI Return Main routine errors
(SWDT) 0? 0
Interrupt processing routine errors
Fig. 61 Watchdog timer by software
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LIST OF PRECAUTIONS
Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; * connect a bypass capacitor (approx. 0.1 F) between pins VDD and VSS at the shortest distance, * equalize its wiring in width and length, and * use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 k (connect this resistor to CNVSS/ VPP pin as close as possible). In addtion, the MCU may be replaced with mask ROM version without the need to remove the resistor from the circuit and without any adverse effect on operation. Register initial values 1 The initial value of the following registers are undefined after system is released from reset. After system is released from reset, set initial values. * Register Z (2 bits) * Register D (3 bits) * Register E (8 bits) Register initial values 2 The initial value of the following registers are undefined at RAM backup. After system is returned from RAM back-up, set initial values. * Register Z (2 bits) * Register X (4 bits) * Register Y (4 bits) * Register D (3 bits) * Register E (8 bits) Stack registers (SKS) Stack registers (SKs) are eight identical registers, so that subroutines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be careful not to over the stack when performing these operations together. Prescaler Stop counting and then execute the TABPS instruction to read from prescaler data. Stop counting and then execute the TPSAB instruction to set prescaler data.
Timer count source Stop timer 1, 2 and LC counting to change its count source. Reading the count value Stop timer 1 or 2 counting and then execute the data read instruction (TAB1, TAB2) to read its data. Writing to the timer Stop timer 1, 2 or LC counting and then execute the data write instruction (T1AB, T2AB, TLCA) to write its data. Writing to reload register R1, R2H When writing data to reload register R1, reload register R2H while timer 1 or timer 2 is operating, avoid a timing when timer 1 or timer 2 underflows.
10
Timer 2 Avoid a timing when timer 2 underflows to stop timer 2 at PWM output function used. When "H" interval extension function of the PWM signal is set to be "valid", set "1" or more to reload register R2H. Timer 3 Stop timer 3 counting to change its count source. Timer input/output pin Set the port C output latch to "0" to output the PWM signal from C/CNTR pin.
11
12
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13
Prescaler and Timer 1 count start timing and count time when operation starts Count starts from the first rising edge of the count source (2) after Prescaler and Timer 1 operations start (1). Time to first underflow (3) is shorter (for up to 1 period of the count source) than time among next underflow (4) by the timing to start the timer and count source operations after count starts. When selecting CNTR input as the count source of Timer 1, Timer 1 operates synchronizing with the falling edge of CNTR input.
(2) Count Source Count Source
Selecting CNTR input falling edge
Watchdog timer * The watchdog timer function is valid after system is released from reset. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously, and clear the WEF flag to "0" to stop the watchdog timer function. * The watchdog timer function is valid after system is returned from the power down state. When not using the watchdog timer function, execute the DWDT instruction and the WRST instruction continuously every system is returned from the power down state, and stop the watchdog timer function. * When the watchdog timer function and power down function are used at the same time, execute the WRST instruction before system enters into the power down state and initialize the flag WDF1.
15 16
Timer Value
3
2
1
0
3
2
1
0
3
2
Timer Underflow signal (3) (1) Timer Start (4)
Multifunction * Be careful that the output of port D5 can be used even when INT pin is selected. The threshold value is different between port D5 and INT. Accordingly, be careful when the input of both is used. * Be careful that the "H" output of port C can be used even when output of CNTR pin are selected.
17
Fig. 62 Timer count start timing and count time when operation starts (Prescaler and Timer 1)
14
Program counter Make sure that the PCH does not specify after the last page of the built-in ROM.
Timer 2 and Timer LC count start timing and count time when operation starts Count starts from the rising edge (2) after the first falling edge of the count source, after Timer 2 and Timer LC operations start (1). Time to first underflow (3) is different from time among next underflow (4) by the timing to start the timer and count source operations after count starts.
(2) Count Source
Timer Value
3
2
1
0
3
2
1
0
3
Timer Underflow Signal (3) (1) Timer Start (4)
Fig. 63 Timer count start timing and count time when operation starts (Timer 2 and Timer LC)
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18
D5/INT pin Note [1] on bit 3 of register I1 When the input of the INT pin is controlled with the bit 3 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 3 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 64) and then, change the bit 3 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 64). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 64).
Note on bit 2 of register I1 When the interrupt valid waveform of the D5/INT pin is changed with the bit 2 of register I1 in software, be careful about the following notes. * Depending on the input state of the D5/INT pin, the external 0 interrupt request flag (EXF0) may be set when the bit 2 of register I1 is changed. In order to avoid the occurrence of an unexpected interrupt, clear the bit 0 of register V1 to "0" (refer to Figure 66) and then, change the bit 2 of register I1. In addition, execute the SNZ0 instruction to clear the EXF0 flag to "0" after executing at least one instruction (refer to Figure 66). Also, set the NOP instruction for the case when a skip is performed with the SNZ0 instruction (refer to Figure 66).
***
LA 4 TV1A LA 8 TI1A NOP SNZ0 NOP
; (02) ; The SNZ0 instruction is valid ........... ; (12) ; Control of INT pin input is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
LA 4 TV1A LA 12 TI1A NOP SNZ0 NOP
***
; (02) ; The SNZ0 instruction is valid ........... ; Interrupt valid waveform is changed ........................................................... ; The SNZ0 instruction is executed (EXF0 flag cleared) ...........................................................
***
: these bits are not used here. Fig. 64 External 0 interrupt program example-1 Note [2] on bit 3 of register I1 When the bit 3 of register I1 is cleared to "0", the RAM back-up mode is selected and the input of INT pin is disabled, be careful about the following notes. * When the key-on wakeup function of INT pin is not used (register K20 = "0"), clear bits 2 and 3 of register I1 before system enters to the power down mode. (refer to Figure 65).
: these bits are not used here. Fig. 66 External 0 interrupt program example-3
LA 0 TI1A DI EPOF POF2
***
; (002) ; Input of INT disabled ........................
; Power down mode
: these bits are not used here. Fig. 65 External 0 interrupt program example-2
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19
POF and POF2 instructions When the POF or POF2 instruction is executed continuously after the EPOF instruction, system enters the power down state. Note that system cannot enter the power down state when executing only the POF or POF2 instruction. Be sure to disable interrupts by executing the DI instruction before executing the EPOF instruction and the POF or POF2 instruction continuously. Power-on reset When the built-in power-on reset circuit is used, set the time for the supply voltage to rise from 0 V to the minimum voltage of recommended operating conditions to 100 s or less. If the rising time exceeds 100 s, connect a capacitor between the RESET pin and VSS at the shortest distance, and input "L" level to RESET pin until the value of supply voltage reaches the minimum operating voltage.
22
Clock control Execute the CRCK instruction in the initial setting routine of program (executing it in address 0 in page 0 is recommended). The oscillation circuit by the CRCK instruction can be selected only once. On-chip oscillator The clock frequency of the on-chip oscillator depends on the supply voltage and the operation temperature range. Be careful that variable frequencies when designing application products. Also, the oscillation stabilize wait time after system is released from reset is generated by the on-chip oscillator clock. When considering the oscillation stabilize wait time after system is released from reset, be careful that the variable frequency of the on-chip oscillator clock. External clock When the external signal clock is used as the source oscillation (f(XIN)), note that the power down mode (POF and POF2 instructions) cannot be used. Difference between Mask ROM version and One Time PROM version Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an electrical property by difference of a manufacture process, builtin ROM, and a layout pattern. * a characteristic value * a margin of operation * the amount of noise-proof * noise radiation, etc., Accordingly, be careful of them when swithcing. Note on Power Source Voltage When the power source voltage value of a microcomputer is less than the value which is indicated as the recommended operating conditions, the microcomputer does not operate normally and may perform unstable operation. In a system where the power source voltage drops slowly when the power source voltage drops or the power supply is turned off, reset a microcomputer when the supply voltage is less than the recommended operating conditions and design a system not to cause errors to the system by this unstable operation.
23
20
24 21
Voltage drop detection circuit (only in H version) The voltage drop detection circuit detection voltage of this product is set up lower than the minimum value of the supply voltage of the recommended operating conditions. When the supply voltage of a microcomputer falls below to the minimum value of recommended operating conditions and regoes up (ex. battery exchange of an application product), depending on the capacity value of the bypass capacitor added to the power supply pin, the following case may cause program failure (Figure 67); supply voltage does not fall below to VRST-, and its voltage re-goes up with no reset. In such a case, please design a system which supply voltage is once reduced below to VRST- and re-goes up after that.
25
26
VDD Recommended operatng condition min.value + VRST - VRST
No reset Program failure may occur.
VDD Recommended operatng condition min.value + VRST - VRST Reset Fig. 67 VDD and VRST-
Normal operation
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CONTROL REGISTERS
Interrupt control register V1 V13 V12 V11 V10 Timer 2 interrupt enable bit Timer 1 interrupt enable bit Not used External 0 interrupt enable bit 0 1 0 1 0 1 0 1 at reset : 00002 at power down : 00002 R/W TAV1/TV1A
Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) This bit has no function, but read/write is enabled. Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) R/W TAV2/TV2A
Interrupt control register V2 V23 V22 V21 V20 Not used Not used Not used Timer 3 interrupt enable bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/W TAI1/TI1A
Interrupt control register I1 I13 INT pin input control bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
INT pin input disabled INT pin input enabled Falling waveform/"L" level ("L" level is recognized with the SNZI0 instruction) Rising waveform/"H" level ("H" level is recognized with the SNZI0 instruction) One-sided edge detected Both edges detected Timer 1 count start synchronous circuit not selected Timer 1 count start synchronous circuit selected R/W TAMR/ TMRA
I12
Interrupt valid waveform for INT pin/ return level selection bit (Note 3)
I11 I10
INT pin edge detection circuit control bit INT pin Timer 1 count start synchronous circuit selection bit
Clock control register MR MR3 Operation mode selection bits MR2
at reset : 11002 MR3 MR2 0 0 0 1 1 0 1 1 MR1 MR0 0 0 0 1 1 0 1 1
at power down : state retained Operation mode
Through mode Frequency divided by 2 mode Frequency divided by 4 mode Frequency divided by 8 mode System clock f(RING) f(XIN) f(XCIN) Not available (Note 4)
MR3 System clock selection bits (Note 3) MR2
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: When the contents of I12 and I13 are changed, the external interrupt request flag (EXF0) may be set. 3: The stopped clock cannot be selected for system clock. 4: "11" cannot be set to the low-order 2 bits (MR1, MR0) of register MR.
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Clock control register RG RG2 RG1 RG0 Sub-clock (f(XCIN)) control bit (Note 2) Main-clock (f(XIN)) control bit (Note 2) On-chip oscillator (f(RING)) control bit (Note 2) 0 1 0 1 0 1
at reset : 0002
W TRGA Sub-clock (f(XCIN)) oscillation available, ports D6 and D7 not selected Sub-clock (f(XCIN)) oscillation stop, ports D6 and D7 selected Main clock (f(XIN)) oscillation available Main clock (f(XIN)) oscillation stop On-chip oscillator (f(RING)) oscillation available On-chip oscillator (f(RING)) oscillation stop at power down : state retained W TPAA
Timer control register PA PA0 Prescaler control bit 0 1
at reset : 02 Stop (state retained) Operating
at power down : 02
Timer control register W1 W13 W12 W11 Timer 1 count source selection bits (Note 4) Timer 1 count auto-stop circuit selection bit (Note 3) Timer 1 control bit
at reset : 00002 0 1 0 1 W11 W10 0 0 0 1 1 0 1 1
at power down : state retained
R/W TAW1/TW1A
W10
Timer 1 count auto-stop circuit not selected Timer 1 count auto-stop circuit selected Stop (state retained) Operating Count source PWM signal (PWMOUT) Prescaler output (ORCLK) Timer 3 underflow signal (T3UDF) CNTR input R/W TAW2/TW2A
Timer control register W2 W23 W22 W21 W20 CNTR pin output control bit PWM signal interrupt valid waveform/ return level selection bit Timer 2 control bit Timer 2 count soruce selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : 00002
CNTR pin output invalid CNTR pin output valid PWM signal "H" interval expansion function invalid PWM signal "H" interval expansion function valid Stop (state retained) Operating XIN input Prescaler output (ORCLK)/2 signal output
Timer control register W3 W33 W32 W31 Timer 3 count value selection bits W30 Timer 3 count auto-stop circuit selection bit Timer 3 control bit
at reset : 00002 0 1 0 1 W31 W30 0 0 0 1 1 0 1 1
at power down : state retained
R/W TAW3/TW3A
XCIN input Prescaler output (ORCLK) Stop (Initial state) Operating Count value Underflow occurs every 8192 counts Underflow occurs every 16384 counts Underflow occurs every 32768 counts Underflow occurs every 65536 counts
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: The oscillation circuit selected for system clock cannot be stopped. 3: This function is valid only when the timer 1 count start synchronous circuit is selected (I10="1"). 4: Port C output is invalid when CNTR input is selected for the timer 1 count source.
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Timer control register W4 W43 W42 W41 W40 Timer LC control bit Timer LC count source selection bit CNTR output auto-control circuit selection bit CNTR pin input count edge selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAW4/TW4A
Stop (state retained) Operating Bit 4 (T34) of timer 3 System clock (STCK) CNTR output auto-control circuit not selected CNTR output auto-control circuit selected Falling edge Rising edge
LCD control register L1 L13 L12 L11 LCD duty and bias selection bits L10 Internal dividing resistor for LCD power supply selection bit (Note 2) LCD control bit 0 1 0 1
at reset : 00002 2r 3, 2r 2 r 3, r 2 Stop Operating Duty
at power down : state retained
R/W TAL1/TL1A
L11 L10 0 0 0 1 1 0 1 1
Bias Not available 1/2 1/3 1/3 W TL2A
1/2 1/3 1/4
LCD control register L2 L23 L22 L21 L20 SEG0/VLC3 pin function switch bit (Note 3) SEG1/VLC2 pin function switch bit (Note 4) SEG2/VLC1 pin function switch bit (Note 4) Internal dividing resistor for LCD power supply control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
SEG0 VLC3 SEG1 VLC2 SEG2 VLC1 Internal dividing resistor valid Internal dividing resistor invalid
LCD control register L3 L33 L32 L31 L30 P23/SEG20 pin function switch bit P22/SEG19 pin function switch bit P21/SEG18 pin function switch bit P20/SEG17 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG20 P23 SEG19 P22 SEG18 P21 SEG17 P20
at power down : state retained
W TL3A
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: "r (resistor) multiplied by 3" is used at 1/3 bias, and "r multiplied by 2" is used at 1/2 bias. 3: VLC3 is connected to VDD internally when SEG0 pin is selected. 4: Use internal dividing resistor when SEG1 and SEG2 pins are selected.
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LCD control register C1 C13 C12 C11 C10 P03/SEG24 pin function switch bit P02/SEG23 pin function switch bit P01/SEG22 pin function switch bit P00/SEG21 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG24 P03 SEG23 P02 SEG22 P01 SEG21 P00
at power down : state retained
W TC1A
LCD control register C2 C23 C22 C21 C20 P13/SEG28 pin function switch bit P12/SEG27 pin function switch bit P11/SEG26 pin function switch bit P10/SEG25 pin function switch bit 0 1 0 1 0 1 0 1
at reset : 11112 SEG28 P13 SEG27 P12 SEG26 P11 SEG25 P10
at power down : state retained
W TC2A
Pull-up control register PU0 PU03 PU02 PU01 PU00 Port P03 pull-up transistor control bit Port P02 pull-up transistor control bit Port P01 pull-up transistor control bit Port P00 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU0/ TPU0A
Pull-up control register PU1 PU13 PU12 PU11 PU10 Port P13 pull-up transistor control bit Port P12 pull-up transistor control bit Port P11 pull-up transistor control bit Port P10 pull-up transistor control bit 0 1 0 1 0 1 0 1
at reset : 00002 Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON
at power down : state retained
R/W TAPU1/ TPU1A
Note: "W" represents write enabled.
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Port output structure control register FR0 FR03 FR02 FR01 FR00 Ports P12, P13 output structure selection bit Ports P10, P11 output structure selection bit Ports P02, P03 output structure selection bit Ports P00, P01 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
W TFR0A
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output at reset : 00002 at power down : state retained W TFR1A
Port output structure control register FR1 FR13 FR12 FR11 FR10 Port D3 output structure selection bit Port D2 output structure selection bit Port D1 output structure selection bit Port D0 output structure selection bit 0 1 0 1 0 1 0 1
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output W TFR2A
Port output structure control register FR2 FR23 FR22 FR21 FR20 Ports P22, P23 output structure selection bit Ports P20, P21 output structure selection bit Port D5 output structure selection bit Port D4 output structure selection bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output N-channel open-drain output CMOS output
Note: "W" represents write enabled.
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Key-on wakeup control register K0 K03 K02 K01 K00 Port P12, P13 key-on wakeup control bit (Note 3) Port P10, P11 key-on wakeup control bit (Note 2) Port P02, P03 key-on wakeup control bit Port P00, P01 key-on wakeup control bit 0 1 0 1 0 1 0 1
at reset : 00002
at power down : state retained
R/W TAK0/ TK0A
Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used R/W TAK1/ TK1A
Key-on wakeup control register K1 K13 K12 K11 K10 Ports P12, P13 return condition selection bit (Note 3) Ports P12, P13 valid waveform/level selection bit (Note 3) Ports P10, P11 return condition selection bit (Note 2) Ports P10, P11 valid waveform/level selection bit (Note 2) 0 1 0 1 0 1 0 1
at reset : 00002 Returned by edge Returned by level
at power down : state retained
Falling waveform/"L" level Rising waveform/"H" level Returned by edge Returned by level Falling waveform/"L" level Rising waveform/"H" level at reset : 00002 at power down : state retained R/W TAK2/ TK2A
Key-on wakeup control register K2 K23 K22 K21 K20 Not used Not used INT pin return condition selection bit INT pin key-on wakeup control bit 0 1 0 1 0 1 0 1
This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. Returned by level Returned by edge Key-on wakeup invalid Key-on wakeup valid
Notes 1: "R" represents read enabled, and "W" represents write enabled. 2: To be invalid (K02 = "0") key-on wakeup of ports P10 and P11, set the registers K10 and K11 to "0". 3: To be invalid (K03 = "0") key-on wakeup of ports P12 and P13, set the registers K12 and K13 to "0".
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4556 Group
INSTRUCTIONS
The 4556 Group has the 124 (123) instructions. Each instruction is described as follows; (1) Index list of instruction function (2) Machine instructions (index by alphabet) (3) Machine instructions (index by function) (4) Instruction code table Symbol A B DR E V1 V2 I1 MR RG PA W1 W2 W3 W4 L1 L2 L3 C1 C2 PU0 PU1 FR0 FR1 FR2 K0 K1 K2 X Y Z DP PC PCH PCL SK SP CY UPTF RPS R1 R3 R2L R2H RLC Contents Register A (4 bits) Register B (4 bits) Register DR (3 bits) Register E (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Clock control register MR (4 bits) Clock control register RG (3 bits) Timer control register PA (1 bit) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) LCD control register L1 (4 bits) LCD control register L2 (4 bits) LCD control register L3 (4 bits) LCD control register C1 (4 bits) LCD control register C2 (4 bits) Pull-up control register PU0 (4 bits) Pull-up control register PU1 (4 bits) Port output structure control register FR0 (4 bits) Port output structure control register FR1 (4 bits) Port output structure control register FR2 (4 bits) Key-on wakeup control register K0 (4 bits) Key-on wakeup control register K1 (4 bits) Key-on wakeup control register K2 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 8) Stack pointer (3 bits) Carry flag High-order bit reference enable flag Prescaler reload register (8 bits) Timer 1 reload register (8 bits) Timer 3 reload register (8 bits) Timer 2 reload register (8 bits) Timer 2 reload register (8 bits) Timer LC reload register (4 bits)
SYMBOL
The symbols shown below are used in the following list of instruction function and the machine instructions.
Symbol PS T1 T2 T3 TLC T1F T2F T3F WDF1 WEF INTE EXF0 P D P0 P1 P2 C x y z p n i j A3A2A1A0
Contents Prescaler Timer 1 Timer 2 Timer 3 Timer LC Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag Power down flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (4 bits) Port C (1 bit) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before "?" Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p6 p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x
? () -- M(DP) a p, a C + x
Note : Some instructions of the 4556 Group has the skip function to unexecute the next described instruction. The 4556 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accordingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes "1" if the TABP p, RT, or RTS instruction is skipped.
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4556 Group
INDEX LIST OF INSTRUCTION FUNCTION
GroupMnemonic ing TAB TBA TAY TYA TEAB (A) (B) Function GroupMnemonic ing XAMI j (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 TMA j (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15 LA n (A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) at (UPTF) = 0 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 at (UPTF) = 1 (DR2) (0) (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) + (CY) (CY) Carry An (A) (A) + n n = 0 to 15 AND OR SC RC SZC CMA RAR (A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 Function
(B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A)
Register to register transfer
TABE
(B) (E7-E4) (A) (E3-E0) TABP p
TDA TAD
(DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0
TAZ
(A1, A0) (Z1, Z0) (A3, A2) 0
TAX TASP
(A) (X) (A2-A0) (SP2-SP0) AM
LXY x, y
(X) x x = 0 to 15 (Y) y y = 0 to 15
RAM addresses
LZ z INY DEY TAM j
(Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
RAM to register transfer
XAM j
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
XAMD j
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
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Arithmetic operation
(A3) 0
RAM to register transfer
AMC
4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
GroupMnemonic ing SB j (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 SZB j (Mj(DP)) = 0 ? j = 0 to 3 SNZ0 V10 = 0: (EXF0) = 1 ? (EXF0) 0 V10 = 1: SNZ0 = NOP SNZI0 I12 = 1 : (INT) = "H" ? I12 = 0 : (INT) = "L" ? TAV1 TV1A TAV2 BL p, a (PCH) p (PCL) a6-a0 BLA p (PCH) p (PCL) (DR2-DR0, A3-A0) TI1A BM a (SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 TPAA TAW1 TW1A TAW2 TW2A BMLA p (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0) RTI (PC) (SK(SP)) (SP) (SP) - 1 RT (PC) (SK(SP)) (SP) (SP) - 1 RTS (PC) (SK(SP)) (SP) (SP) - 1 TPSAB (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) TABPS (B) (TPS7-TPS4) (A) (TPS3-TPS0) TAW3 (A) (W3) (W3) (A) (A) (W4) (W4) (A) (PA) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (I1) (A) TV2A TAI1 (V2) (A) (A) (I1) (A) (V1) (V1) (A) (A) (V2) Function GroupMnemonic ing DI EI RB j (INTE) 0 (INTE) 1 Function
Bit operation
Comparison operation
SEAM SEA n
(A) = (M(DP)) ? (A) = n ? n = 0 to 15
Ba
(PCL) a6-a0
Subroutine operation
Branch operation
BML p, a
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0
Timer operation
Interrupt operation
TW3A TAW4 TW4A
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
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Return operation
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4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TAB1 (B) (T17-T14) (A) (T13-T10) RD T1AB (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) TAB2 (B) (T27-T24) (A) (T23-T20) T2AB (R27-R24) (B) (T27-T24) (B) (R23-R20) (A) (T23-T20) (A) TAPU0 T2HAB (R2H7-R2H4) (B) (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A) (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A) RC oscillator selected (A) (MR) (MR) (A) (RG) (A) SCP (C) 1 RCP SD (D(Y)) 1 (Y) = 0 to 7 SZD (D(Y)) = 0 ? (Y) = 0 to 5 (C) 0 (D(Y)) 0 (Y) = 0 to 7 Function GroupMnemonic ing CLD (D) 1 Function
Timer operation
(R2H3-R2H0) (A) TR1AB (R17-R14) (B) (R13-R10) (A) T2R2L (T27-T24) (R2L7-R2L4) (T23-T20) (R2L3-R2L0) (LC) (A) (RLC) (A)
Input/Output operation Clock operation
TPU0A TAPU1 TPU1A TAK0 TK0A TAK1
TLCA
SNZT1
V12 = 0: (T1F) = 1 ? (T1F) 0 V12 = 1: SNZT1 = NOP
TK1A TAK2
SNZT2
V13 = 0: (T2F) = 1 ? (T2F) 0 V13 = 1: SNZT2 = NOP TFR0A TK2A
SNZT3
V20 = 0: (T3F) = 1 ? (T3F) 0 V20 = 1: SNZT3 = NOP TFR2A TFR1A
IAP0
(A) (P0) CRCK (P0) (A) TAMR TMRA TRGA (A) (P1) (P1) (A) (A) (P2) (P2) (A)
Input/Output operation
OP0A IAP1 OP1A IAP2 OP2A
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4556 Group
INDEX LIST OF INSTRUCTION FUNCTION (continued)
Grouping Mnemonic TAL1 TL1A (A) (L1) (L1) (A) (L2) (A) (L3) (A) (C1) (A) (C2) (A) (PC) (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? Stop of watchdog timer function enabled System reset (WDF1) = 1 ? (WDF1) 0 RUPT SUPT SVDE (Note) (UPTF) 0 (UPTF) 1 At power down mode, voltage drop detection circuit valid Function
LCD operation Other operation
TL2A TL3A TC1A TC2A NOP POF POF2 EPOF SNZP DWDT SRST WRST
Note: The SVDE instruction can be used only for the H version.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET)
A n (Add n and accumulator)
Instruction code D9 0 0 0 1 1 0 n n n D0 n
2
0
6
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Overflow = 0
1
Operation:
(A) (A) + n n = 0 to 15
Grouping: Arithmetic operation Description: Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation.
AM (Add accumulator and Memory)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 0
2
0
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) + (M(DP))
Grouping: Arithmetic operation Description: Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
AMC (Add accumulator, Memory and Carry)
Instruction code D9 0 0 0 0 0 0 1 0 1 D0 1
2
0
0
B
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
(A) (A) + (M(DP)) + (CY) (CY) Carry
Grouping: Arithmetic operation Description: Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY.
AND (logical AND between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 0
2
0
1
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A) AND (M(DP))
Grouping: Arithmetic operation Description: Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A.
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4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
B a (Branch to address a)
Instruction code D9 0 1 1 D0 a6 a5 a4 a3 a2 a1 a0
2
1
8 +a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PCL) a6 to a0
Grouping: Branch operation Description: Branch within a page : Branches to address a in the identical page. Note: Specify the branch address within the page including this instruction.
BL p, a (Branch Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 1 1 D0 p4 p3 p2 p1 p0
2
0 2
E +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(PCH) p (PCL) a6 to a0
Grouping: Branch operation Description: Branch out of a page : Branches to address a in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H.
BLA p (Branch Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 0 1 0 0 0 0 D0 0
2
0 2
1 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 p4 0
p3 p2 p1 p0 2
p 16
(PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Branch operation Description: Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H.
BM a (Branch and Mark to address a in page 2)
Instruction code D9 0 1 0 D0 a6 a5 a4 a3 a2 a1 a0
2
1
a
a
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Note: Subroutine extending from page 2 to another page can also be called with the BM instruction when it starts on page 2. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
BML p, a (Branch and Mark Long to address a in page p)
Instruction code D9 0 1 Operation: 0 0 1 1 0 D0 p4 p3 p2 p1 p0
2
0 2
C +p p +a
p
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 a6 a5 a4 a3 a2 a1 a0 2
a 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) a6-a0
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address a in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
BMLA p (Branch and Mark Long to address (D) + (A) in page p)
Instruction code D9 0 1 Operation: 0 0 0 0 1 1 0 0 0 0 D0 0
2
0 2
3 p
0
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
2
p5 p4 0
p3 p2 p1 p0 2
p 16
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (PCL) (DR2-DR0, A3-A0)
Grouping: Subroutine call operation Description: Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Note: p is 0 to 31 for M34556M4/M4H and p is 0 to 63 for M34556M8/M8H/G8/G8H. Be careful not to over the stack because the maximum level of subroutine nesting is 8.
CLD (CLear port D)
Instruction code D9 0 0 0 0 0 1 0 0 0 D0 1
2
0
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D) 1
Grouping: Input/Output operation Description: Sets (1) to port D.
CMA (CoMplement of Accumulator)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 0
2
0
1
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (A)
Grouping: Arithmetic operation Description: Stores the one's complement for register A's contents in register A.
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4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
CRCK (Clock select: Rc oscillation ClocK)
Instruction code D9 1 0 1 0 0 1 1 0 1 D0 1
2
2
9
B 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
RC oscillation circuit selected
Grouping: Clock control operation Description: Selects the RC oscillation circuit for main clock f(XIN).
DEY (DEcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 1 1 D0 1
2
0
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(Y) (Y) - 1
Grouping: RAM addresses Description: Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed.
DI (Disable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 0
2
0
0
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(INTE) 0
Grouping: Interrupt control operation Description: Clears (0) to interrupt enable flag INTE, and disables the interrupt. Note: Interrupt is disabled by executing the DI instruction after executing 1 machine cycle.
DWDT (Disable WatchDog Timer)
Instruction code D9 1 0 1 0 0 1 1 1 0 D0 0
2
2
9
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Stop of watchdog timer function enabled
Grouping: Other operation Description: Stops the watchdog timer function by the WRST instruction after executing the DWDT instruction.
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4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
EI (Enable Interrupt)
Instruction code D9 0 0 0 0 0 0 0 1 0 D0 1
2
0
0
5 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(INTE) 1
Grouping: Interrupt control operation Description: Sets (1) to interrupt enable flag INTE, and enables the interrupt. Note: Interrupt is enabled by executing the EI instruction after executing 1 machine cycle.
EPOF (Enable POF instruction)
Instruction code D9 0 0 0 1 0 1 1 0 1 D0 1
2
0
5
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
POF instruction, POF2 instruction valid
Grouping: Other operation Description: Makes the immediate after POF instruction or POF2 instruction valid by executing the EPOF instruction.
IAP0 (Input Accumulator from port P0)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 0
2
2
6
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P0)
Grouping: Input/Output operation Description: Transfers the input of port P0 to register A.
IAP1 (Input Accumulator from port P1)
Instruction code D9 1 0 0 1 1 0 0 0 0 D0 1
2
2
6
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (P1)
Grouping: Input/Output operation Description: Transfers the input of port P1 to register A.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
IAP2 (Input Accumulator from port P2)
Instruction code D9 1 0 0 1 1 0 0 0 1 D0 0
2
2
6
2 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (P2)
Grouping: Input/Output operation Description: Transfers the input of port P2 to register A.
INY (INcrement register Y)
Instruction code D9 0 0 0 0 0 1 0 0 1 D0 1
2
0
1
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(Y) (Y) + 1
Grouping: RAM addresses Description: Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed.
LA n (Load n in Accumulator)
Instruction code D9 0 0 0 1 1 1 n n n D0 n
2
0
7
n
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(A) n n = 0 to 15
Grouping: Arithmetic operation Description: Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped.
LXY x, y (Load register X and Y with x and y)
Instruction code D9 1 1 D0 x3 x2 x1 x0 y3 y2 y1 y0
2
3
x
y
Number of words
16
Number of cycles 1
Flag CY -
Skip condition Continuous description
1
Operation:
(X) x x = 0 to 15 (Y) y y = 0 to 15
Grouping: RAM addresses Description: Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped.
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4556 Group
MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
LZ z (Load register Z with z)
Instruction code D9 0 0 0 1 0 0 1 0 D0 z1 z0
2
0
4
8 +z 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Z) z z = 0 to 3
Grouping: RAM addresses Description: Loads the value z in the immediate field to register Z.
NOP (No OPeration)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 0
2
0
0
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (PC) + 1
Grouping: Other operation Description: No operation; Adds 1 to program counter value, and others remain unchanged.
OP0A (Output port P0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 0
2
2
2
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P0) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P0.
OP1A (Output port P1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 0 D0 1
2
2
2
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P1) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P1.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
OP2A (Output port P2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 0 0 1 D0 0
2
2
2
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(P2) (A)
Grouping: Input/Output operation Description: Outputs the contents of register A to port P2.
OR (logical OR between accumulator and memory)
Instruction code D9 0 0 0 0 0 1 1 0 0 D0 12 0 1 9 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (A) OR (M(DP))
Grouping: Arithmetic operation Description: Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A.
POF (Power OFf)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 0
2
0
0
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Transition to clock operating mode
Grouping: Other operation Description: Puts the system in clock operating mode by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
POF2 (Power OFf2)
Instruction code D9 0 0 0 0 0 0 1 0 0 D0 0
2
0
0
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
Transition to RAM back-up mode
Grouping: Other operation Description: Puts the system in RAM back-up state by executing the POF2 instruction after executing the EPOF instruction. Note: If the EPOF instruction is not executed before executing this instruction, this instruction is equivalent to the NOP instruction.
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RAR (Rotate Accumulator Right)
Instruction code D9 0 0 0 0 0 1 1 1 0 D0 1
2
0
1
D
Number of words
16
Number of cycles 1
Flag CY 0/1
Skip condition -
1
Operation:
CY A3A2A1A0
Grouping: Arithmetic operation Description: Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right.
RB j (Reset Bit)
Instruction code D9 0 0 0 1 0 0 1 1 j D0 j
2
0
4
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 0 j = 0 to 3
Grouping: Bit operation Description: Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
RC (Reset Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 0
2
0
0
6
Number of words
16
Number of cycles 1
Flag CY 0
Skip condition -
1
Operation:
(CY) 0
Grouping: Arithmetic operation Description: Clears (0) to carry flag CY.
RCP (Reset Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 0
2
2
8
C
Number of words
16
Number of cycles 1
Flag CY 0
Skip condition -
1
Operation:
(C) 0
Grouping: Input/Output operation Description: Clears (0) to carry flag CY.
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RD (Reset port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 0
2
0
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 0 However, (Y) = 0 to 7
Grouping: Input/Output operation Description: Clears (0) to a bit of port D specified by register Y.
RT (ReTurn from subroutine)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 0
2
0
4
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine.
RTI (ReTurn from Interrupt)
Instruction code D9 0 0 0 1 0 0 0 1 1 D0 0
2
0
4
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt.
RTS (ReTurn from subroutine and Skip)
Instruction code D9 0 0 0 1 0 0 0 1 0 D0 1
2
0
4
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition Skip at uncondition
1
Operation:
(PC) (SK(SP)) (SP) (SP) - 1
Grouping: Return operation Description: Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
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RUPT (Reset UPTF flag)
Instruction code D9 0 0 0 1 0 1 1 0 0 D0 0
2
0
5
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(UPTF) 0
Grouping: Other operation Description: Clears (0) to the high-order bit reference enable flag.
SB j (Set Bit)
Instruction code D9 0 0 0 1 0 1 1 1 j D0 j
2
0
5
C +j 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(Mj(DP)) 1 j = 0 to 3
Grouping: Bit operation Description: Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP).
SC (Set Carry flag)
Instruction code D9 0 0 0 0 0 0 0 1 1 D0 1
2
0
0
7
Number of words
16
Number of cycles 1
Flag CY 1
Skip condition -
1
Operation:
(CY) 1
Grouping: Arithmetic operation Description: Sets (1) to carry flag CY.
SCP (Set Port C)
Instruction code D9 1 0 1 0 0 0 1 1 0 D0 1
2
2
8
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C) 1
Grouping: Input/Output operation Description: Sets (1) to port C.
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SD (Set port D specified by register Y)
Instruction code D9 0 0 0 0 0 1 0 1 0 D0 1
2
0
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(D(Y)) 1 (Y) = 0 to 7
Grouping: Input/Output operation Description: Sets (1) to a bit of port D specified by register Y.
SEA n (Skip Equal, Accumulator with immediate data n)
Instruction code D9 0 0 Operation: 0 0 0 0 0 1 1 1 0 1 0 n 1 n 0 n D0 1 n
2
0 0
2 7
5
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (A) = n n = 0 to 15
2
2
(A) = n ? n = 0 to 15
n 16 Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
SEAM (Skip Equal, Accumulator with Memory)
Instruction code D9 0 0 0 0 1 0 0 1 1 D0 0
2
0
2
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (A) = (M(DP))
1
Operation:
(A) = (M(DP)) ?
Grouping: Comparison operation Description: Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP).
SNZ0 (Skip if Non Zero condition of external 0 interrupt request flag)
Instruction code D9 0 0 0 0 1 1 1 0 0 D0 0
2
0
3
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V10 = 0: (EXF0) = 1
1
Operation:
V10 = 0: (EXF0) = 1 ? (EXF0) 0 V10 = 1: SNZ0 = NOP (V10 : bit 0 of the interrupt control register V1)
Grouping: Interrupt operation Description: When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is "1." When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction.
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SNZI0 (Skip if Non Zero condition of external 0 Interrupt input pin)
Instruction code D9 0 0 0 0 1 1 1 0 1 D0 02 0 3 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition I12 = 0 : (INT) = "L" I12 = 1 : (INT) = "H"
Operation:
I12 = 0 : (INT) = "L" ? I12 = 1 : (INT) = "H" ? (I12 : bit 2 of the interrupt control register I1)
Grouping: Interrupt operation Description: When I12 = 0 : Skips the next instruction when the level of INT pin is "L." Executes the next instruction when the level of INT pin is "H." When I12 = 1 : Skips the next instruction when the level of INT pin is "H." Executes the next instruction when the level of INT pin is "L." Number of words
16
SNZP (Skip if Non Zero condition of Power down flag)
Instruction code D9 0 0 0 0 0 0 0 0 1 D0 1
2
0
0
3
Number of cycles 1
Flag CY -
Skip condition (P) = 1
1
Operation:
(P) = 1 ?
Grouping: Other operation Description: Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Executes the next instruction when the P flag is "0."
SNZT1 (Skip if Non Zero condition of Timer 1 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 0
2
2
8
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V12 = 0: (T1F) = 1
1
Operation:
V12 = 0: (T1F) = 1 ? (T1F) 0 V12 = 1: SNZT1 = NOP (V12 = bit 2 of interrupt control register V1)
Grouping: Timer operation Description: When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is "1." When the T1F flag is "0," executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction.
SNZT2 (Skip if Non Zero condition of Timer 2 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 0 D0 1
2
2
8
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V13 = 0: (T2F) = 1
1
Operation:
V13 = 0: (T2F) = 1 ? (T2F) 0 V13 = 1: SNZT2 = NOP (V13 = bit 3 of interrupt control register V1)
Grouping: Timer operation Description: When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is "1." When the T2F flag is "0," executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction.
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SNZT3 (Skip if Non Zero condition of Timer 3 interrupt request flag)
Instruction code D9 1 0 1 0 0 0 0 0 1 D0 0
2
2
8
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition V20 = 0: (T3F) = 1
1
Operation:
V20 = 0: (T3F) = 1 ? (T3F) 0 V20 = 1: SNZT3 = NOP (V20 = bit 0 of interrupt control register V2)
Grouping: Timer operation Description: When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is "1." When the T3F flag is "0," executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction.
SRST (System ReSeT)
Instruction code D9 0 0 0 0 0 0 0 0 0 D0 1
2
0
0
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
System reset occurrence
Grouping: Other operation Description: System reset occurs.
SUPT (Set UPTF flag)
Instruction code D9 0 0 0 1 0 1 1 0 0 D0 1
2
0
5
9 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(UPTF) 1
Grouping: Other operation Description: Sets (1) to high-order bit reference enable flag.
SVDE (Se Voltage Detector Enable flag)
Instruction code D9 1 0 1 0 0 1 0 0 1 D0 1
2
2
9
3 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
Voltage drop detection circuit valid at powerdown mode.
Grouping: Other operation Description: Voltage drop detection circuit is valid at powerdown mode (clock operating mode, RAM back-up mode) Note: This instruction can be used only for H version.
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SZB j (Skip if Zero, Bit)
Instruction code D9 0 0 0 0 1 0 0 0 j D0 j
2
0
2
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Mj(DP)) = 0 j = 0 to 3
1
Operation:
(Mj(DP)) = 0 ? j = 0 to 3
Grouping: Bit operation Description: Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1."
SZC (Skip if Zero, Carry flag)
Instruction code D9 0 0 0 0 1 0 1 1 1 D0 1
2
0
2
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (CY) = 0
1
Operation:
(CY) = 0 ?
Grouping: Arithmetic operation Description: Skips the next instruction when the contents of carry flag CY is "0." After skipping, the CY flag remains unchanged. Executes the next instruction when the contents of the CY flag is "1."
SZD (Skip if Zero, port D specified by register Y)
Instruction code D9 0 0 Operation: 0 0 0 0 0 0 1 1 0 0 0 1 1 0 0 1 D0 0
2
0 0
2 2
4
Number of words
16
Number of cycles 2
Flag CY -
Skip condition (D(Y)) = 0
(Y) = 0 to 7
2
12
B 16
(D(Y)) = 0 ? (Y) = 0 to 7
Grouping: Input/Output operation Description: Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when the bit is "1." Note: (Y) = 0 to 5. Do not execute this instruction if values except above are set to register Y.
T1AB (Transfer data to timer 1 and register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 0
2
2
3
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(T17-T14) (B) (R17-R14) (B) (T13-T10) (A) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1. Transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
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T2AB (Transfer data to timer 2 and register R2L from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 0 0 D0 1
2
2
3
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(R2L7-R2L4) (B) (T27-T24) (B) (R2L3-R2L0) (A) (T23-T20) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.
T2HAB (Transfer data to register R2H from Accumulator and register B)
Instruction code D9 1 0 1 0 0 1 0 1 0 D0 0
2
2
9
4 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(R2H7-R2H4) (B) (R2H3-R2H0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2H. Transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2H.
T2R2L (Transfer data to timer 2 from register R2L)
Instruction code D9 1 0 1 0 0 1 0 1 0 D0 12 2 9 5 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(T27-T20) (R2L7-R2L0)
Grouping: Timer operation Description: Transfers the contents of reload register R2L to timer 2.
TAB (Transfer data to Accumulator from register B)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 02 0 1 E 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A) (B)
Grouping: Register to register transfer Description: Transfers the contents of register B to register A.
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TAB1 (Transfer data to Accumulator and register B from timer 1)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 0
2
2
7
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T17-T14) (A) (T13-T10)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T17-T14) of timer 1 to register B. Transfers the low-order 4 bits (T13-T10) of timer 1 to register A.
TAB2 (Transfer data to Accumulator and register B from timer 2)
Instruction code D9 1 0 0 1 1 1 0 0 0 D0 1
2
2
7
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (T27-T24) (A) (T23-T20)
Grouping: Timer operation Description: Transfers the high-order 4 bits (T27-T24) of timer 2 to register B. Transfers the low-order 4 bits (T23-T20) of timer 2 to register A.
TABE (Transfer data to Accumulator and register B from register E)
Instruction code D9 0 0 0 0 1 0 1 0 1 D0 02 0 2 A 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(B) (E7-E4) (A) (E3-E0)
Grouping: Register to register transfer Description: Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits of register E to register A.
TABP p (Transfer data to Accumulator and register B from Program memory in page p)
Instruction code D9 0 0 1 0 D0 p5 p4 p3 p2 p1 p0 2 0
8 +p
p 16
Number of words 1
Number of cycles 3
Flag CY -
Skip condition -
Operation: (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) at (UPTF) = 0 at (UPTF) = 1 (B) (ROM(PC))7-4 (DR2) (0) (A) (ROM(PC))3-0 (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1
Grouping: Arithmetic operation Description: UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in ad-dress (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. Note: p is 0 to 31 for M34556M4/M4H, and p is 0 to 63 for M34556M8/M8H/G8/G8H. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
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TABPS (Transfer data to Accumulator and register B from PreScaler)
Instruction code D9 1 0 0 1 1 1 0 1 0 D0 12 2 7 5 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(B) (TPS7-TPS4) (A) (TPS3-TPS0)
Grouping: Timer operation Description: Transfers the high-order 4 bits (TPS7- TPS4) of prescaler to register B, and transfers the low-order 4 bits (TPS3-TPS0) of prescaler to register A.
TAD (Transfer data to Accumulator from register D)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 1
2
0
5
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (DR2-DR0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Note: When this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
TAI1 (Transfer data to Accumulator from register I1)
Instruction code D9 1 0 0 1 0 1 0 0 1 D0 1
2
2
5
3
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (I1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register I1 to register A.
TAK0 (Transfer data to Accumulator from register K0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 0
2
2
5
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K0)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K0 to register A.
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TAK1 (Transfer data to Accumulator from register K1)
Instruction code D9 1 0 0 1 0 1 1 0 0 D0 1
2
2
5
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K1)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K1 to register A.
TAK2 (Transfer data to Accumulator from register K2)
Instruction code D9 1 0 0 1 0 1 1 0 1 D0 0
2
2
5
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (K2)
Grouping: Input/Output operation Description: Transfers the contents of key-on wakeup control register K2 to register A.
TAL1 (Transfer data to Accumulator from register L1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 0
2
2
4
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (L1)
Grouping: LCD control operation Description: Transfers the contents of LCD control register L1 to register A.
TAM j (Transfer data to Accumulator from Memory)
Instruction code D9 1 0 1 1 0 0 j j j D0 j
2
2
C
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
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TAMR (Transfer data to Accumulator from register MR)
Instruction code D9 1 0 0 1 0 1 0 0 1 D0 0
2
2
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (MR)
Grouping: Clock operation Description: Transfers the contents of clock control register MR to register A.
TAPU0 (Transfer data to Accumulator from register PU0)
Instruction code D9 1 0 0 1 0 1 0 1 1 D0 12 2 5 7 16 1 Operation: (A) (PU0) 1 - - Number of words Number of cycles Flag CY Skip condition
Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU0 to register A.
TAPU1 (Transfer data to Accumulator from register PU1)
Instruction code D9 1 0 0 1 0 1 1 1 1 D0 02 2 5 E 16 1 Operation: (A) (PU1) 1 - - Grouping: Input/Output operation Description: Transfers the contents of pull-up control register PU1 to register A. Number of words Number of cycles Flag CY Skip condition
TASP (Transfer data to Accumulator from Stack Pointer)
Instruction code D9 0 0 0 1 0 1 0 0 0 D0 0
2
0
5
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A2-A0) (SP2-SP0) (A3) 0
Grouping: Register to register transfer Description: Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Note: After this instruction is executed, "0" is stored to the bit 3 (A3) of register A.
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TAV1 (Transfer data to Accumulator from register V1)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 0
2
0
5
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V1)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V1 to register A.
TAV2 (Transfer data to Accumulator from register V2)
Instruction code D9 0 0 0 1 0 1 0 1 0 D0 1
2
0
5
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (V2)
Grouping: Interrupt operation Description: Transfers the contents of interrupt control register V2 to register A.
TAW1 (Transfer data to Accumulator from register W1)
Instruction code D9 1 0 0 1 0 0 1 0 1 D0 1
2
2
4
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W1)
Grouping: Timer operation Description: Transfers the contents of timer control register W1 to register A.
TAW2 (Transfer data to Accumulator from register W2)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 0
2
2
4
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (W2)
Grouping: Timer operation Description: Transfers the contents of timer control register W2 to register A.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAW3 (Transfer data to Accumulator from register W3)
Instruction code D9 1 0 0 1 0 0 1 1 0 D0 1
2
2
4
D 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (W3)
Grouping: Timer operation Description: Transfers the contents of timer control register W3 to register A.
TAW4 (Transfer data to Accumulator from register W4)
Instruction code D9 1 0 0 1 0 0 1 1 1 D0 0
2
2
4
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(A) (W4)
Grouping: Timer operation Description: Transfers the contents of timer control register W4 to register A.
TAX (Transfer data to Accumulator from register X)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 0
2
0
5
2
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (X)
Grouping: Register to register transfer Description: Transfers the contents of register X to register A.
TAY (Transfer data to Accumulator from register Y)
Instruction code D9 0 0 0 0 0 1 1 1 1 D0 1
2
0
1
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (Y)
Grouping: Register to register transfer Description: Transfers the contents of register Y to register A.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TAZ (Transfer data to Accumulator from register Z)
Instruction code D9 0 0 0 1 0 1 0 0 1 D0 12 0 5 3 16 Number of words 1 Number of cycles 1 Flag CY - Skip condition -
Operation:
(A1, A0) (Z1, Z0) (A3, A2) 0
Grouping: Register to register transfer Description: Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Note: After this instruction is executed, "0" is stored to the high-order 2 bits (A3, A2) of register A.
TBA (Transfer data to register B from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 1 D0 0
2
0
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(B) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register B.
TC1A (Transfer data to register C1 from Accumulator)
Instruction code D9 1 0 1 0 1 0 1 0 0 D0 0
2
2
A
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C1) (A)
Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control register C1.
TC2A (Transfer data to register C2 from Accumulator)
Instruction code D9 1 0 1 0 1 0 1 0 0 D0 1
2
2
A
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(C2) (A)
Grouping: LCD control operation Description: Transfers the contents of register A to the LCD control register C2.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TDA (Transfer data to register D from Accumulator and register B)
Instruction code D9 0 0 0 0 1 0 1 0 0 D0 1
2
0
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(DR2-DR0) (A2-A0)
Grouping: Register to register transfer Description: Transfers the low-order 3 bits (A2-A0) of register A to register D.
TEAB (Transfer data to register E from Accumulator and register B)
Instruction code D9 0 0 0 0 0 1 1 0 1 D0 0
2
0
1
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(E7-E4) (B) (E3-E0) (A)
Grouping: Register to register transfer Description: Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E.
TFR0A (Transfer data to register FR0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 0
2
2
2
8
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR0.
TFR1A (Transfer data to register FR1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 0 D0 1
2
2
2
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(FR1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR1.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TFR2A (Transfer data to register FR2 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 0 1 D0 0
2
2
2
A 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(FR2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to the port output structure control register FR2.
TI1A (Transfer data to register I1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 1
2
2
1
7
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(I1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register I1.
TK0A (Transfer data to register K0 from Accumulator)
Instruction code D9 1 0 0 0 0 1 1 0 1 D0 1
2
2
1
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K0.
TK1A (Transfer data to register K1 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 0
2
2
1
4
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K1.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TK2A (Transfer data to register K2 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 0 D0 1
2
2
1
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(K2) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to keyon wakeup control register K2.
TL1A (Transfer data to register L1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 1 D0 0
2
2
0
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(L1) (A)
Grouping: LCD control operation Description: Transfers the contents of register A to LCD control register L1.
TL2A (Transfer data to register L2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 1 D0 1
2
2
0
B
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(L2) (A)
Grouping: LCD control operation Description: Transfers the contents of register A to LCD control register L2.
TL3A (Transfer data to register L3 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 0 D0 0
2
2
0
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(L3) (A)
Grouping: LCD control operation Description: Transfers the contents of register A to LCD control register L3.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TLCA (Transfer data to register LC from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 0 D0 1
2
2
0
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(LC) (A) (RLC) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer LC and reload register RLC.
TMA j (Transfer data to Memory from Accumulator)
Instruction code D9 1 0 1 0 1 1 j j j D0 j
2
2
B
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
TMRA (Transfer data to register MR from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 1 1 D0 0
2
2
1
6
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(MR) (A)
Grouping: Other operation Description: Transfers the contents of register A to clock control register MR.
TPAA (Transfer data to register PA from Accumulator)
Instruction code D9 1 0 1 0 1 0 1 0 1 D0 0
2
2
A
A
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PA0) (A0)
Grouping: Timer operation Description: Transfers the contents of lowermost bit (A0) register A to timer control register PA.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TPSAB (Transfer data to Pre-Scaler from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 0 1 0 D0 1
2
2
3
5
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS.
TPU0A (Transfer data to register PU0 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 0 D0 1
2
2
2
D
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU0) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU0.
TPU1A (Transfer data to register PU1 from Accumulator)
Instruction code D9 1 0 0 0 1 0 1 1 1 D0 0
2
2
2
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(PU1) (A)
Grouping: Input/Output operation Description: Transfers the contents of register A to pullup control register PU1.
TR1AB (Transfer data to register R1 from Accumulator and register B)
Instruction code D9 1 0 0 0 1 1 1 1 1 D0 1
2
2
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(R17-R14) (B) (R13-R10) (A)
Grouping: Timer operation Description: Transfers the contents of register B to the high-order 4 bits (R17-R14) of reload register R1, and the contents of register A to the low-order 4 bits (R13-R10) of reload register R1.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TRGA (Transfer data to register RG from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 0 0 D0 1
2
2
0
9
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(RG) (A)
Grouping: Clock control operation Description: Transfers the contents of register A to register RG.
TV1A (Transfer data to register V1 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 1
2
0
3
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(V1) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V1.
TV2A (Transfer data to register V2 from Accumulator)
Instruction code D9 0 0 0 0 1 1 1 1 1 D0 0
2
0
3
E 16
Number of words 1
Number of cycles 1
Flag CY -
Skip condition -
Operation:
(V2) (A)
Grouping: Interrupt operation Description: Transfers the contents of register A to interrupt control register V2.
TW1A (Transfer data to register W1 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 0
2
2
0
E
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W1) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W1.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
TW2A (Transfer data to register W2 from Accumulator)
Instruction code D9 1 0 0 0 0 0 1 1 1 D0 1
2
2
0
F
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W2) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W2.
TW3A (Transfer data to register W3 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 0
2
2
1
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W3) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W3.
TW4A (Transfer data to register W4 from Accumulator)
Instruction code D9 1 0 0 0 0 1 0 0 0 D0 1
2
2
1
1
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(W4) (A)
Grouping: Timer operation Description: Transfers the contents of register A to timer control register W4.
TYA (Transfer data to register Y from Accumulator)
Instruction code D9 0 0 0 0 0 0 1 1 0 D0 0
2
0
0
C
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(Y) (A)
Grouping: Register to register transfer Description: Transfers the contents of register A to register Y.
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MACHINE INSTRUCTIONS (INDEX BY ALPHABET) (continued)
WRST (Watchdog timer ReSeT)
Instruction code D9 1 0 1 0 1 0 0 0 0 D0 0
2
2
A
0
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (WDF1) = 1
1
Operation:
(WDF1) = 1 ? (WDF1) 0
Grouping: Other operation Description: Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is "1." When the WDF1 flag is "0," executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction.
XAM j (eXchange Accumulator and Memory data)
Instruction code D9 1 0 1 1 0 1 j j j D0 j
2
2
D
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition -
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
XAMD j (eXchange Accumulator and Memory data and Decrement register Y and skip)
Instruction code D9 1 0 1 1 1 1 j j j D0 j
2
2
F
j
Number of words
16
Number of cycles 1
Flag CY -
Skip condition (Y) = 15
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. D0 Number of words
16
XAMI j (eXchange Accumulator and Memory data and Increment register Y and skip)
Instruction code D9 1 0 1 1 1 0 j j j j
2
2
E
j
Number of cycles 1
Flag CY -
Skip condition (Y) = 0
1
Operation:
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1
Grouping: RAM to register transfer Description: After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. when the contents of register Y is not 0, the next instruction is executed.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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MACHINE INSTRUCTIONS (INDEX BY TYPES)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAB TBA TAY TYA 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0
01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy
1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1
(A) (B) (B) (A) (A) (Y) (Y) (A) (E7-E4) (B) (E3-E0) (A) (B) (E7-E4) (A) (E3-E0) (DR2-DR0) (A2-A0) (A2-A0) (DR2-DR0) (A3) 0 (A1, A0) (Z1, Z0) (A3, A2) 0 (A) (X) (A2-A0) (SP2-SP0) (A3) 0 (X) x x = 0 to 15 (Y) y y = 0 to 15 (Z) z z = 0 to 3 (Y) (Y) + 1 (Y) (Y) - 1
Register to register transfer
TEAB TABE TDA TAD TAZ TAX TASP LXY x, y
x3 x2 x1 x0 y3 y2 y1 y0
RAM addresses
LZ z INY DEY
0 0 0
0 0 0
0 0 0
1 0 0
0 0 0
0 1 1
1 0 0
0 0 1
z1 z0 1 1 1 1
048 +z 013 017
1 1 1
1 1 1
TAM j
1
0
1
1
0
0
j
j
j
j
2Cj
1
1
(A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) - 1 (A) (M(DP)) (X) (X)EXOR(j) j = 0 to 15 (Y) (Y) + 1 (M(DP)) (A) (X) (X)EXOR(j) j = 0 to 15
XAM j
1
0
1
1
0
1
j
j
j
j
2Dj
1
1
RAM to register transfer
XAMD j
1
0
1
1
1
1
j
j
j
j
2Fj
1
1
XAMI j
1
0
1
1
1
0
j
j
j
j
2Ej
1
1
TMA j
1
0
1
0
1
1
j
j
j
j
2Bj
1
1
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4556 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - Continuous description - (Y) = 0 (Y) = 15
- - - - - - - - - - - -
Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of register B to the high-order 4 bits (E7-E4) of register E, and the contents of register A to the low-order 4 bits (E3-E0) of register E. Transfers the high-order 4 bits (E7-E4) of register E to register B, and low-order 4 bits (E3-E0) of register E to register A. Transfers the contents of the low-order 3 bits (A2-A0) of register A to register D. Transfers the contents of register D to the low-order 3 bits (A2-A0) of register A. Transfers the contents of register Z to the low-order 2 bits (A1, A0) of register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to the low-order 3 bits (A2-A0) of register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. When the contents of register Y is not 15, the next instruction is executed. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. When the contents of register Y is not 0, the next instruction is executed. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between register X and the value j in the immediate field, and stores the result in register X.
- - -
-
-
-
-
(Y) = 15
-
(Y) = 0
-
-
-
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4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 LA n 0 0 0 1 1 1 n n n n
07n
1
1
(A) n n = 0 to 15 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0, A3-A0) at (UPTF) = 0 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 at (UPTF) = 1 (DR2) (0) (DR1, DR0) (ROM(PC))9, 8 (B) (ROM(PC))7-4 (A) (ROM(PC))3-0 (PC) (SK(SP)) (SP) (SP) - 1 (A) (A) + (M(DP)) (A) (A) + (M(DP)) +(CY) (CY) Carry (A) (A) + n n = 0 to 15
TABP p
0
0
1
0
p5 p4 p3 p2 p1 p0
08p +p
1
3
Arithmetic operation
AM AMC An
0 0 0
0 0 0
0 0 0
0 0 1
0 0 1
0 0 0
1 1 n
0 0 n
1 1 n
0 1 n
00A 00B 06n
1 1 1
1 1 1
AND OR SC RC SZC CMA RAR SB j
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1 0
0 0 0 0 1 0 0 0 0 1
1 1 0 0 0 1 1 1 0 0
1 1 0 0 1 1 1 1 1 0
0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 0 0 j j j
0 1 1 0 1 0 1 j j j
018 019 007 006 02F 01C 01D 05C +j 04C +j 02j
1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1
(A) (A) AND (M(DP)) (A) (A) OR (M(DP)) (CY) 1 (CY) 0 (CY) = 0 ? (A) (A) CY A3A2A1A0 (Mj(DP)) 1 j = 0 to 3 (Mj(DP)) 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ?
Bit operation
RB j SZB j
SEAM
0
0
0
0
1
0
0
1
1
0
026
1
1
Comparison operation
SEA n
0 0
0 0
0 0
0 1
1 1
0 1
0 n
1 n
0 n
1 n
025 07n
2
2
(A) = n ? n = 0 to 15
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 112 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
Continuous description -
-
Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. UPTF = 0: Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 9 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used. UPTF = 1: Transfers bits 9, 8 to register D, bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, be careful not to over the stack because 1 stage of stack register is used.
-
- - Overflow = 0
-
Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY remains unchanged.
0/1 Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. - Adds the value n in the immediate field to register A, and stores a result in register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Executes the next instruction when there is overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the result in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is "0." Stores the one's complement for register A's contents in register A.
- - - - (CY) = 0 - - - - (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP))
- - 1 0 - -
0/1 Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. - - - Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is "0." Executes the next instruction when the contents of bit j of M(DP) is "1." Skips the next instruction when the contents of register A is equal to the contents of M(DP). Executes the next instruction when the contents of register A is not equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field. Executes the next instruction when the contents of register A is not equal to the value n in the immediate field.
-
(A) = n
-
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 113 of 142
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Ba BL p, a 0 0 1 BLA p 0 1 BM a 0 1 0 1 1 a6 a5 a4 a3 a2 a1 a0 1 1 p4 p3 p2 p1 p0
18a +a 0Ep +p 2pa +p +a 010 2pp +p 1aa
1 2
1 2
(PCL) a6-a0 (PCH) p (Note) (PCL) a6-a0
Branch operation
p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 0 1 0 0 0 0 0
2
2
(PCH) p (Note) (PCL) (DR2-DR0, A3-A0)
p6 p5 p4 0 1 0
p3 p2 p1 p0
a6 a5 a4 a3 a2 a1 a0
1
1
Subroutine operation
(SP) (SP) + 1 (SK(SP)) (PC) (PCH) 2 (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) a6-a0 (SP) (SP) + 1 (SK(SP)) (PC) (PCH) p (Note) (PCL) (DR2-DR0,A3-A0) (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1 (PC) (SK(SP)) (SP) (SP) - 1
BML p, a
0 1
0
1
1
0
p4 p3 p2 p1 p0
0Cp +p 2pa +p +a 030 2pp +p 046
2
2
p6 p5 a6 a5 a4 a3 a2 a1 a0 0 0 0 1 1 0 0 0 0 0
BMLA p
0 1
2
2
p6 p5 p4 0
p3 p2 p1 p0
RTI
0
0
0
1
0
0
0
1
1
0
1
1
Return operation
RT
0
0
0
1
0
0
0
1
0
0
044
1
2
RTS
0
0
0
1
0
0
0
1
0
1
045
1
2
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 114 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
- -
- -
Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p.
-
-
Branch out of a page : Branches to address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Call the subroutine in page 2 : Calls the subroutine at address a in page 2.
-
-
Call the subroutine : Calls the subroutine at address a in page p.
-
-
Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p.
-
-
Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous description of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine.
-
-
Skip at uncondition
-
Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 115 of 142
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DI EI SNZ0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 1 1 0 0 0 0 0 1 0
004 005 038
1 1 1
1 1 1
(INTE) 0 (INTE) 1 V10 = 0: (EXF0) = 1 ? (EXF0) 0 V10 = 1: SNZ0 = NOP I12 = 1 : (INT) = "H" ? I12 = 0 : (INT) = "L" ?
SNZI0
0
0
0
0
1
1
1
0
1
0
03A
1
1
Interrupt operation
TAV1 TV1A TAV2 TV2A TAI1 TI1A
0 0 0 0 1 1
0 0 0 0 0 0
0 0 0 0 0 0
1 0 1 0 1 0
0 1 0 1 0 0
1 1 1 1 1 1
0 1 0 1 0 0
1 1 1 1 0 1
0 1 0 1 1 1
0 1 1 0 1 1
054 03F 055 03E 253 217
1 1 1 1 1 1
1 1 1 1 1 1
(A) (V1) (V1) (A) (A) (V2) (V2) (A) (A) (I1) (I1) (A)
Note: p is 0 to 31 for M34556M4/M4H. p is 0 to 63 for M34556M8/M8H/G8/G8H.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 116 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
- - V10 = 0: (EXF0) = 1
- - -
Clears (0) to interrupt enable flag INTE, and disables the interrupt. Sets (1) to interrupt enable flag INTE, and enables the interrupt. When V10 = 0 : Clears (0) to the EXF0 flag and skips the next instruction when external 0 interrupt request flag EXF0 is "1." When the EXF0 flag is "0," executes the next instruction. When V10 = 1 : This instruction is equivalent to the NOP instruction. (V10: bit 0 of interrupt control register V1) When I12 = 1 : Skips the next instruction when the level of INT pin is "H." (I12: bit 2 of interrupt control register I1) When I12 = 0 : Skips the next instruction when the level of INT pin is "L."
(INT) = "H" However, I12 = 1 (INT) = "L" However, I12 = 0 - - - - - -
- -
- - - - - -
Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 117 of 142
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TPAA TAW1 TW1A TAW2 TW2A TAW3 TW3A TAW4 TW4A TABPS TPSAB 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 1 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 1 1 0 0 1 1 1
2AA 24B 20E 24C 20F 24D 210 24E 211 275 235
1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1
(PA) (A) (A) (W1) (W1) (A) (A) (W2) (W2) (A) (A) (W3) (W3) (A) (A) (W4) (W4) (A) (B) (TPS7-TPS4) (A) (TPS3-TPS0) (RPS7-RPS4) (B) (TPS7-TPS4) (B) (RPS3-RPS0) (A) (TPS3-TPS0) (A) (B) (T17-T14) (A) (T13-T10) (R17-R14) (B) (T17-T14) (B) (R13-R10) (A) (T13-T10) (A) (B) (T27-T24) (A) (T23-T20) (R2L7-R2L4) (B) (T27-T24) (B) (R2L3-R2L0) (A) (T23-T20) (A) (R2H7-R2H4) (B) (R2H3-R2H0) (A) (R17-R14) (B) (R13-R10) (A) (T27-T20) (R2L7-R2L0) (LC) (A) (RLC) (A) V12 = 0: (T1F) = 1 ? (T1F) 0 V12 = 1: SNZT1 = NOP V13 = 0: (T2F) = 1 ? (T2F) 0 V13 = 1: SNZT2 = NOP V20 = 0: (T3F) = 1 ? (T3F) 0 V20 = 1: SNZT3 = NOP
TAB1
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
0 0
270 230
1 1
1 1
Timer operation
T1AB
TAB2 T2AB
1 1
0 0
0 0
1 0
1 1
1 1
0 0
0 0
0 0
1 1
271 231
1 1
1 1
T2HAB TR1AB T2R2L TLCA SNZT1
1 1 1 1 1
0 0 0 0 0
1 0 1 0 1
0 0 0 0 0
0 1 0 0 0
1 1 1 0 0
0 1 0 1 0
1 1 1 1 0
0 1 0 0 0
0 1 1 1 0
294 23F 295 20D 280
1 1 1 1 1
1 1 1 1 1
SNZT2
1
0
1
0
0
0
0
0
0
1
281
1
1
SNZT3
1
0
1
0
0
0
0
0
1
0
282
1
1
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 118 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - -
- - - - - - - - - - -
Transfers the contents of register A to timer control register PA. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the high-order 4 bits of prescaler to register B, and transfers the low-order 4 bits of prescaler to register A. Transfers the contents of register B to the high-order 4 bits of prescaler and prescaler reload register RPS, and transfers the contents of register A to the low-order 4 bits of prescaler and prescaler reload register RPS. Transfers the high-order 4 bits of timer 1 to register B, and transfers the low-order 4 bits of timer 1 to register A. Transfers the contents of register B to the high-order 4 bits of timer 1 and timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 and timer 1 reload register R1.
- -
- -
- -
- -
Transfers the high-order 4 bits of timer 2 to register B, and transfers the low-order 4 bits of timer 2 to register A. Transfers the contents of register B to the high-order 4 bits of timer 2 and timer 2 reload register R2L, and transfers the contents of register A to the low-order 4 bits of timer 2 and timer 2 reload register R2L.
- - - - V12 = 0: (T1F) = 1
- - - - -
Transfers the contents of register B to the high-order 4 bits of timer 2 reload register R2H, and transfers the contents of register A to the low-order 4 bits of timer 2 reload register R2H. Transfers the contents of register B to the high-order 4 bits of timer 1 reload register R1, and transfers the contents of register A to the low-order 4 bits of timer 1 reload register R1. Transfers the contents of timer 2 reload register R2L to timer 2. Transfers the contents of register A to timer LC and timer LC reload register RLC. When V12 = 0 : Clears (0) to the T1F flag and skips the next instruction when timer 1 interrupt request flag T1F is "1". When the T1F flag is "0", executes the next instruction. When V12 = 1 : This instruction is equivalent to the NOP instruction. (V12: bit 2 of interrupt control register V1) When V13 = 0 : Clears (0) to the T2F flag and skips the next instruction when timer 2 interrupt request flag T2F is "1". When the T2F flag is "0", executes the next instruction. When V13 = 1 : This instruction is equivalent to the NOP instruction. (V13: bit 3 of interrupt control register V1) When V20 = 0 : Clears (0) to the T3F flag and skips the next instruction when timer 3 interrupt request flag T3F is "1". When the T3F flag is "0", executes the next instruction. When V20 = 1 : This instruction is equivalent to the NOP instruction. (V20: bit 0 of interrupt control register V2)
V13 = 0: (T2F) =1
-
V20 = 0: (T3F) = 1
-
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 119 of 142
4556 Group
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 IAP0 OP0A IAP1 OP1A IAP2 OP2A CLD RD SD SZD 1 1 1 1 1 1 0 0 0 0 0 RCP SCP TAPU0 TPU0A TAPU1 TPU1A TAK0 TK0A TAK1 TK1A TAK2 TK2A TFR0A TFR1A TFR2A 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 0 0 1 1 1 1 1 1 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 1 0 1 1 0 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 1 1 1 1 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 0 1 1 0 0 1 0 1 0
260 220 261 221 262 222 011 014 015 024 02B 28C 28D 257 22D 25E 22E 256 21B 259 214 25A 215 228 229 22A
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (P0) (P0) (A) (A) (P1) (P1) (A) (A) (P2) (P2) (A) (D) 1 (D(Y)) 0 (Y) = 0 to 7 (D(Y)) 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 5 (C) 0 (C) 1 (A) (PU0) (PU0) (A) (A) (PU1) (PU1) (A) (A) (K0) (K0) (A) (A) (K1) (K1) (A) (A) (K2) (K2) (A) (FR0) (A) (FR1) (A) (FR2) (A)
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
Input/Output operation
page 120 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - (D(Y)) = 0 However, (Y)=0 to 5 - - - - - - - - - - - - - - -
- - - - - - - - - -
Transfers the input of port P0 to register A. Outputs the contents of register A to port P0. Transfers the input of port P1 to register A. Outputs the contents of register A to port P1. Transfers the input of port P2 to register A. Outputs the contents of register A to port P2. Sets (1) to all port D. Clears (0) to a bit of port D specified by register Y. Sets (1) to a bit of port D specified by register Y. Skips the next instruction when a bit of port D specified by register Y is "0." Executes the next instruction when a bit of port D specified by register Y is "1." Clears (0) to port C. Sets (1) to port C. Transfers the contents of pull-up control register PU0 to register A. Transfers the contents of register A to pull-up control register PU0. Transfers the contents of pull-up control register PU1 to register A. Transfers the contents of register A to pull-up control register PU1. Transfers the contents of key-on wakeup control register K0 to register A. Transfers the contents of register A to key-on wakeup control register K0. Transfers the contents of key-on wakeup control register K1 to register A. Transfers the contents of register A to key-on wakeup control register K1. Transfers the contents of key-on wakeup control register K2 to register A. Transfers the contents of register A to key-on wakeup control register K2. Transferts the contents of register A to port output structure control register FR0. Transferts the contents of register A to port output structure control register FR1. Transferts the contents of register A to port output structure control register FR2.
- - - - - - - - - - - - - - -
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 121 of 142
4556 Group
MACHINE INSTRUCTIONS (INDEX BY TYPES) (continued)
Number of words
Parameter
Number of cycles
Instruction code Mnemonic
Hexadecimal notation
Function
Type of instructions
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 TAL1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 1 1 1 1 0 0 1 0 0 1 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 0 1 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 1 0
24A 20A 20B 20C 2A8 2A9 29B 252 216 209 000 002 008 05B 003 2A0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
(A) (L1) (L1) (A) (L2) (A) (L3) (A) (C1) (A) (C2) (A) RC oscillator selected (A) (MR) (MR) (A) (RG) (A) (PC) (PC) + 1 Transition to clock operating mode Transition to RAM back-up mode POF, POF2 instructions valid (P) = 1 ? (WDF1) = 1 ? (WDF1) 0 Stop of watchdog timer function enabled System reset (UPTF) 0 (UPTF) 1 At power down mode, voltage drop detection circuit valid
LCD operation Clock operation Other operation
TL1A TL2A TL3A TC1A TC2A CRCK TAMR TMRA TRGA NOP POF POF2 EPOF SNZP WRST
DWDT SRST RUPT SUPT SVDE
1 0 0 0 1
0 0 0 0 0
1 0 0 0 1
0 0 1 1 0
0 0 0 0 0
1 0 1 1 1
1 0 1 1 0
1 0 0 0 0
0 0 0 0 1
0 1 0 1 1
29C 001 058 059 293
1 1 1 1 1
1 1 1 1 1
Note: SVDE instruction can be used only in H version.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 122 of 142
4556 Group
Skip condition
Carry flag CY
Datailed description
- - - - - - - - - - - - - - (P) = 1 (WDF1) = 1
- - - - - - - - - - - - - - - -
Transfers the contents of LCD control register L1 to register A. Transfers the contents of register A to LCD control register L1. Transfers the contents of register A to LCD control register L2. Transfers the contents of register A to LCD control register L3. Transfers the contents of register A to LCD control register C1. Transfers the contents of register A to LCD control register C2. Selects the RC oscillation circuit for main clock, stops the on-chip oscillator (internal oscillator). Transfers the contents of clock control regiser MR to register A. Transfers the contents of register A to clock control register MR. Transfers the contents of register A to clock control register RG. No operation; Adds 1 to program counter value, and others remain unchanged. Puts the system in clock operating mode by executing the POF instruction after executing the EPOF instruction. Puts the system in RAM back-up mode by executing the POF2 instruction after executing the EPOF instruction. Makes the immediate after POF or POF2 instruction valid by executing the EPOF instruction. Skips the next instruction when the P flag is "1". After skipping, the P flag remains unchanged. Clears (0) to the WDF1 flag and skips the next instruction when watchdog timer flag WDF1 is "1." When the WDF1 flag is "0", executes the next instruction. Also, stops the watchdog timer function when executing the WRST instruction immediately after the DWDT instruction. Stops the watchdog timer function by the WRST instruction. System reset occurs. Clears (0) to the high-order bit reference enable flag UPTF. Sets (1) to the high-order bit reference enable flag UPTF. Validates the voltage drop detection circuit at power down (clock operating mode and RAM back-up mode).
- - - - -
- - - - -
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 123 of 142
4556 Group
INSTRUCTION CODE TABLE
D9-D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011001100 001101 001110 001111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
010000 011000 010111 011111
00 NOP
01 BLA
02
03
04 - - - - RT
05 TASP TAD TAX TAZ TAV1
06 A 0 A 1 A 2 A 3 A 4 A 5 A 6 A 7 A 8 A 9 A 10 A 11 A 12 A 13 A 14 A 15
07 LA 0 LA 1 LA 2 LA 3 LA 4 LA 5 LA 6 LA 7 LA 8 LA 9 LA 10 LA 11 LA 12 LA 13 LA 14 LA 15
08
09
0A
0B
0C
0D BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML
0E BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
0F BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL
10-17 18-1F BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM B B B B B B B B B B B B B B B B
SZB BMLA 0 SZB 1 SZB 2 SZB 3 SZD SEAn SEAM - - TDA - - - - - - - SNZ0 -
TABP TABP TABP TABP BML 32* 48* 0 16 TABP TABP TABP TABP BML 33* 49* 1 17 TABP TABP TABP TABP BML 34* 50* 2 18 TABP TABP TABP TABP BML 35* 51* 3 19 TABP TABP TABP TABP BML 36* 52* 4 20 TABP TABP TABP TABP BML 37* 53* 5 21 TABP TABP TABP TABP BML 38* 54* 6 22 TABP TABP TABP TABP BML 39* 55* 7 23 TABP TABP TABP TABP BML 40* 56* 8 24 TABP TABP TABP TABP BML 41* 57* 9 25 TABP TABP TABP TABP BML 42* 58* 10 26 TABP TABP TABP TABP BML 43* 59* 11 27 TABP TABP TABP TABP BML 44* 60* 12 28 TABP TABP TABP TABP BML 45* 61* 13 29 TABP TABP TABP TABP BML 46* 62* 14 30 TABP TABP TABP TABP BML 47* 63* 15 31
SRST CLD POF -
SNZP INY DI EI RC SC RD SD - DEY
RTS TAV2 RTI - LZ 0 LZ 1 LZ 2 LZ 3 RB 0 RB 1 RB 2 RB 3 - - RUPT SUPT - EPOF SB 0 SB 1 SB 2 SB 3
POF2 AND - AM AMC TYA - TBA - OR
TEAB TABE SNZI0 - CMA RAR TAB TAY - - - - - - - TV2A
SZC TV1A
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the low-order 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 * * cannot be used in the M3455xM4/M4H.
BL BML BLA BMLA SEA SZD
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INSTRUCTION CODE TABLE (continued)
D9-D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 D3-D0 notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 7 8 9 A B C D E F
Hex.
110000 111111
20 - - - - - - - - - TRGA TL1A
21
22
23
24 - - - - - - - - - -
25 - -
26
27
28
29 - - - SVDE** T2HAB T2R2L - - - - - CRCK
2A WRST - - - - - - - TC1A TC2A TPAA - - - - -
2B TMA 0 TMA 1 TMA 2 TMA 3 TMA 4 TMA 5 TMA 6 TMA 7 TMA 8 TMA 9 TMA 10 TMA 11 TMA 12 TMA 13 TMA 14 TMA 15
2C TAM 0 TAM 1 TAM 2 TAM 3 TAM 4 TAM 5 TAM 6 TAM 7 TAM 8 TAM 9 TAM 10 TAM 11 TAM 12 TAM 13 TAM 14 TAM 15
2D
2E
2F
30-3F
TW3A OP0A T1AB TW4A OP1A T2AB - - TK1A TK2A TMRA TI1A - - - OP2A - - - - - TFR0A TFR1A TFR2A - - TPU0A TPU1A - - - - TPSAB - - - - - - - - -
IAP0 TAB1 SNZT1 IAP1 TAB2 SNZT2 - - - TABPS - - - - - - - - - - SNZT3 - - - - - - - - -
XAM XAMI XAMD LXY 0 0 0 XAM XAMI XAMD LXY 1 1 1 XAM XAMI XAMD LXY 2 2 2 XAM XAMI XAMD LXY 3 3 3 XAM XAMI XAMD LXY 4 4 4 XAM XAMI XAMD LXY 5 5 5 XAM XAMI XAMD LXY 6 6 6 XAM XAMI XAMD LXY 7 7 7 XAM XAMI XAMD LXY 8 8 8 XAM XAMI XAMD LXY 9 9 9 XAM XAMI XAMD LXY 10 10 10 XAM XAMI XAMD LXY 11 11 11 XAM XAMI XAMD LXY 12 12 12 XAM XAMI XAMD LXY 13 13 13 XAM XAMI XAMD LXY 14 14 14 XAM XAMI XAMD LXY 15 15 15
TAMR IAP2 TAI1 - - TAK0 TAPU0 - TAK1 - - - - - - - - - - - - -
TAL1 TAK2 TAW1 TAW2 TAW3 - - -
TL2A TK0A TL3A TLCA TW1A TW2A - - - -
RCP DWDT SCP - - - - -
TAW4 TAPU1 - -
TR1AB
The above table shows the relationship between machine language codes and machine language instructions. D3-D0 show the loworder 4 bits of the machine language code, and D9-D4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked "-." The codes for the second word of a two-word instruction are described below. The second word 1p paaa aaaa 1p paaa aaaa 1p pp00 pppp 1p pp00 pppp 00 0111 nnnn 00 0010 1011 * ** can be used only in the M3455xM4H/M8H/G8H.
BL BML BLA BMLA SEA SZD
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ELECTRICAL CHARACTERISTICS (1) Mask ROM version ABSOLUTE MAXIMUM RATINGS (Mask ROM version)
Symbol VDD VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, D0-D5, RESET, INT, XIN, XCIN Input voltage CNTR Output voltage P0, P1, P2, D0-D7, RESET, CNTR Output voltage C, XOUT, XCOUT Output voltage SEG0-SEG28, COM0-COM3 Power dissipation Operating temperature range Storage temperature range Ta = 25 C Output transistors in cut-off state Conditions Ratings -0.3 to 6.5 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 85 -40 to 125 Unit V V V V V V mW C C
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RECOMMENDED OPERATING CONDITIONS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (when ceramic resonator is used) Conditions f(STCK) 6 MHz f(STCK) 4.4 MHz f(STCK) 2.2 MHz f(STCK) 1.1 MHz VDD Supply voltage (when quartz-crystal/on-chip VDD VRAM VSS VLC3 VIH oscillation is used) Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) "H" level input voltage P0, P1, P2, D0-D5 XIN, XCIN
RESET
Limits Min. 4 2.7 2 1.8 1.8 Typ. Max. 5.5 5.5 5.5 5.5 5.5
Unit V
V
f(STCK) 4.4 MHz at RAM back-up mode
2.7 1.6 0 1.8 0.8VDD 0.7VDD 0.85VDD 0.85VDD 0.8VDD 0 0 0 0 0 VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V
5.5
V V V
VDD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD 0.15VDD -20 -10 -30 -15 -10 -5 -20 -10 24 12 10 4 15 7 5 2 -40 60 60
V V
INT CNTR VIL "L" level input voltage P0, P1, P2, D0-D5 XIN, XCIN
RESET
V
INT CNTR IOH(peak) "H" level peak output current P0, P1, P2, D0-D5 C CNTR IOH(avg) "H" level average output current (Note 2) C IOL(peak) "L" level peak output current CNTR P0, P1, P2, D0-D7, C CNTR
RESET
mA
P0, P1, P2, D0-D5
mA
mA
IOL(avg)
"L" level average output current (Note 2)
P0, P1, P2, D0-D7, C CNTR
RESET
mA
IOH(avg) IOL(avg)
"H" level total average current "L" level total average current
P0, P1, P2, D0-D5, C, CNTR P0, P1, P2, D0-D5, C, CNTR D6, D7, RESET
mA mA
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)*VLC3 At 1/3 bias: VLC1 = (1/3)*VLC3, VLC2 = (2/3)*VLC3 2: The average output current is the average value during 100 ms.
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RECOMMENDED OPERATING CONDITIONS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Through mode Conditions VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V Frequency/2 mode VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4 mode Frequency/8 mode f(XIN) f(XIN) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic oscillation selected, external clock input) Frequency/2 mode Through mode VDD = 4 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 2.7 to 5.5 V VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V Frequency/4 mode Frequency/8 mode f(XCIN) Oscillation frequency (sub-clock) Quartz-crystal oscillator CNTR CNTR VDD = 0 1.8 V 3/f(STCK) f(CNTR) Timer external input frequency tw(CNTR) Timer external input period ("H" and "L" pulse width) TPON Power-on reset circuit valid supply voltage rising time
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Min.
Limits Typ.
Max. 6 4.4 2.2 1.1 6 4.4 2.2 6 4.4 6 4.4 4.8 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8
Unit MHz
VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 1.8 to 5.5 V
VDD = 2.7 to 5.5 V
MHz MHz
VDD = 2 to 5.5 V VDD = 1.8 to 5.5 V VDD = 1.8 to 5.5 V
kHz 50 f(STCK)/6 Hz s 100 s
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at ceramic oscillation (Mask ROM version)
f(STCK) [MHz] 6
at external clock oscillation (Mask ROM version)
f(STCK) [MHz] 4.8
4.4
3.2
1.6 2.2
Recommended operating conditions
1.1 VDD [V]
0.8
Recommended operating conditions
1.8 2 2.7 4.5 5.5 VDD [V]
1.8 2
2.7
4.5
5.5
at RC oscillation (Mask ROM version)
f(STCK) [MHz]
at quartz-crystal oscillation (Mask ROM version)
f(STCK) [kHz]
4.4
Recommended operating conditions
50
Recommended operating conditions
2.7 5.5 VDD [V] 1.8 5.5 VDD [V]
System clock (STCK) operating condition map (Mask ROM version)
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ELECTRICAL CHARACTERISTICS 1
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol VOH Parameter "H" level output voltage P0, P1, P2, D0-D5 VDD = 3 V VOH "H" level output voltage C, CNTR VDD = 5 V VDD = 3 V VOL "L" level output voltage P0, P1, P2, D0-D7, C, CNTR VDD = 3 V VOL "L" level output voltage RESET VDD = 3 V IIH "H" level input current P0, P1, P2, D0-D5, XIN, XCIN, RESET CNTR, INT IIL "L" level input current P0, P1, P2, D0-D5, XIN, XCIN, RESET CNTR, INT RPU Pull-up resistor value P0, P1, RESET VI = 0 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VT+ - VT- Hysteresis CNTR f(RING) f(XIN) On-chip oscillator clock frequency Frequency error (with RC oscillation, error of external R, C not included ) (Note 1) RCOM RSEG RVLC COM output impedance (Note 2) SEG output impedance (Note 2) Internal resistor for LCD power supply VDD = 3 V 10 %, Ta = 25 C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V When dividing resistor 2r 3 selected When dividing resistor 2r 2 selected When dividing resistor r 3 selected When dividing resistor r 2 selected
Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C). 2: The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VSS
Test conditions VDD = 5 V IOH = -10 mA IOH = -3 mA IOH = -5 mA IOH = -1 mA IOH = -20 mA IOH = -6 mA IOH = -10 mA IOH = -3 mA VDD = 5 V IOL = 15 mA IOL = 5 mA IOL = 9 mA IOL = 3 mA VDD = 5 V IOL = 5 mA IOL = 1 mA IOL = 2 mA VI = VDD
Limits Min. 3 4.1 2.1 2.4 3 4.1 2.1 2.4 2 0.9 1.4 0.9 2 0.6 0.9 2 Typ. Max.
Unit V
V
V
V
A
VI = 0 V P0, P1 No pull-up
-2
A
VDD = 5 V VDD = 3 V
30 50
60 120 1 0.4 0.6 0.3 0.2 0.2
125 250
k V V V
VT+ - VT- Hysteresis RESET VT+ - VT- Hysteresis INT
VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V 10 %, Ta = 25 C 200 100
500 250
700 400 17 17
kHz %
1.5 2 1.5 300 200 150 100 2 480 320 240 160
7.5 10 7.5 10 960 640 480 320
k k k
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ELECTRICAL CHARACTERISTICS 2
(Mask ROM version: Ta = -20 C to 85 C, VDD = 1.8 to 5.5 V, unless otherwise noted) Symbol IDD Parameter Supply current at active mode VDD = 5 V Test conditions f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) VDD = 5 V VDD = 3 V Limits Min. Typ. 1.2 1.3 1.6 2.2 0.9 1 1.2 1.6 0.3 0.4 0.5 0.7 50 60 80 120 10 13 19 31 7 8 10 14 5 6 7 8 6 5 0.1 Max. 2.4 2.6 3.2 4.4 1.8 2 2.4 3.2 0.6 0.8 1.0 1.4 100 120 160 240 20 26 38 62 14 16 20 28 10 12 14 16 12 10 2 10 6 mA mA Unit mA
(with a ceramic resonator) f(XIN) = 6 MHz f(RING) = stop f(XCIN) = stop VDD = 5 V f(XIN) = 4 MHz f(RING) = stop f(XCIN) = stop VDD = 3 V f(XIN) = 4 MHz f(RING) = stop f(XCIN) = stop at active mode (with an on-chip oscillator) VDD = 5 V f(XIN) = stop f(RING) = active f(XCIN) = stop VDD = 3 V f(XIN) = stop f(RING) = active f(XCIN) = stop at active mode (with a quartz-crystal oscillator) VDD = 5 V f(XIN) = stop f(RING) = stop f(XCIN) = 32 kHz VDD = 3 V f(XIN) = stop f(RING) = stop at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution) Ta = 25 C VDD = 5 V VDD = 3 V f(XCIN) = 32 kHz f(XCIN) = 32 kHz
A
A
A
A
A A
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(Mask ROM version: Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST- Parameter Detection voltage (reset occurs) (Note 2) Ta = 25 C -20 C Ta < 0 C 0 C Ta < 50 C 50 C Ta 85 C VRST+ Detection voltage (reset release) (Note 3) Ta = 25 C -20 C Ta < 0 C 0 C Ta < 50 C 50 C Ta 85 C VRST+ - VRST- IRST TRST Operation current (Note 4) Detection time (Note 5) VDD = 5 V VDD = 3 V VDD (VRST- - 0.1 V) 50 30 0.2 100 60 1.2 ms Detection voltage hysteresis Test conditions Min. 1.6 1.7 1.4 1.2 1.7 1.8 1.5 1.3 0.1 1.9 Limits Typ. 1.8 Max. 2 2.3 2.2 1.9 2.1 2.4 2.3 2 V V Unit V
A
Notes 1: The voltage drop detection circuit is equipped with only the H version. 2: The detection voltage (VRST-) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 3: The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. 4: In the H version, IRST is added to IDD (power current). 5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- - 0.1 V]. 6: The detection voltages (VRST+, VRST-) are set up lower than the minimum value of the supply voltage of the recommended operating conditions. As for details, refer to the LIST OF PRECAUTIONS.
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(2) One Time PROM version ABSOLUTE MAXIMUM RATINGS (One Time PROM version)
Symbol VDD VI VI VO VO VO Pd Topr Tstg Parameter Supply voltage Input voltage P0, P1, P2, D0-D5, RESET, INT, XIN, XCIN Input voltage CNTR Output voltage P0, P1, P2, D0-D7, RESET, CNTR Output voltage C, XOUT, XCOUT Output voltage SEG0-SEG28, COM0-COM3 Power dissipation Operating temperature range Storage temperature range Ta = 25 C Output transistors in cut-off state Conditions Ratings -0.3 to 4.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 -0.3 to VDD+0.3 300 -20 to 85 -40 to 125 Unit V V V V V V mW C C
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RECOMMENDED OPERATING CONDITIONS 1
(One Time PROM version: Ta = -20 C to 85 C, VDD = 1.8 to 3.6 V, unless otherwise noted) Symbol VDD Parameter Supply voltage (when ceramic resonator is used) Supply voltage (when quartz-crystal/on-chip oscillator is used) VDD VRAM VSS VLC3 VIH Supply voltage (when RC oscillation is used) RAM back-up voltage Supply voltage LCD power supply (Note 1) "H" level input voltage P0, P1, P2, D0-D5 XIN, XCIN
RESET
Conditions f(STCK) 4.4 MHz f(STCK) 2.2 MHz f(STCK) 1.1 MHz
Limits Min. 2.7 2 1.8 1.8 Typ. Max. 3.6 3.6 3.6 3.6
Unit V
VDD
V
f(STCK) 4.4 MHz at RAM back-up mode
2.7 1.6 0 1.8 0.8VDD 0.7VDD 0.85VDD 0.85VDD 0.8VDD 0 0 0 0 0 VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V
3.6
V V V
VDD VDD VDD VDD VDD VDD 0.2VDD 0.3VDD 0.3VDD 0.15VDD 0.15VDD -10 -15 -5 -10 12 4 7 2 -40 60 60
V V
INT CNTR VIL "L" level input voltage P0, P1, P2, D0-D5 XIN, XCIN
RESET
V
INT CNTR IOH(peak) IOH(avg) IOL(peak) "H" level peak output current "H" level average output current (Note 2) "L" level peak output current P0, P1, P2, D0-D5 C, CNTR P0, P1, P2, D0-D5 C, CNTR P0, P1, P2, D0-D7, C, CNTR
RESET
mA mA mA
IOL(avg)
"L" level average output current (Note 2)
P0, P1, P2, D0-D7, C, CNTR
RESET
mA
IOH(avg) IOL(avg)
"H" level total average current "L" level total average current
P0, P1, P2, D0-D5, C, CNTR P0, P1, P2, D0-D5, C, CNTR D6, D7, RESET
mA mA
Notes 1: At 1/2 bias: VLC1 = VLC2 = (1/2)*VLC3 At 1/3 bias: VLC1 = (1/3)*VLC3, VLC2 = (2/3)*VLC3 2: The average output current is the average value during 100 ms.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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4556 Group
RECOMMENDED OPERATING CONDITIONS 2
(One Time PROM version: Ta = -20 C to 85 C, VDD = 1.8 to 3.6 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Frequency/2 mode Through mode Conditions VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V Frequency/4 mode Frequency/8 mode f(XIN) f(XIN) Oscillation frequency (at RC oscillation) (Note) Oscillation frequency (with a ceramic oscillation circuit selected, external clock input) Frequency/2 mode VDD = 2.7 to 3.6 V Through mode VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 2.7 to 3.6 V VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V Frequency/4 mode Frequency/8 mode Quartz-crystal oscillator CNTR CNTR VDD = 0 1.8 V 3/f(STCK) VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 3.6 V f(XCIN) Oscillation frequency VDD = 2 to 3.6 V VDD = 1.8 to 3.6 V VDD = 1.8 to 3.6 V Min. Limits Typ. Max. 4.4 2.2 1.1 6 4.4 2.2 6 4.4 6 4.4 3.2 1.6 0.8 4.8 3.2 1.6 4.8 3.2 4.8 50 kHz MHz MHz Unit MHz
(with a quartz-crystal oscillator) f(CNTR) Timer external input frequency tw(CNTR) Timer external input period ("H" and "L" pulse width) TPON Power-on reset circuit valid supply voltage rising time
f(STCK)/6 Hz s 100 s
Note: The frequency is affected by a capacitor, a resistor and a microcomputer. So, set the constants within the range of the frequency limits.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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at ceramic oscillation (One Time PROM version)
f(STCK) [MHz]
at external clock oscillation (One Time PROM version)
f(STCK) [MHz]
4.4
3.2
1.6 2.2 0.8 1.1
Recommended operating conditions
1.8 2.0 2.7 3.6
VDD [V]
Recommended operating conditions
1.8 2.0 2.7 3.6
VDD [V]
at RC oscillation (One Time PROM version)
f(STCK) [MHz]
at quartz-crystal oscillation (One Time PROM version)
f(STCK) [kHz]
4.4
Recommended operating conditions
50
Recommended operating conditions
2.7 3.6 VDD [V] 1.8 3.6 VDD [V]
System clock (STCK) operating condition map (One Time PROM version)
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
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ELECTRICAL CHARACTERISTICS
(One Time PROM version: Ta = -20 C to 85 C, VDD = 1.8 to 3.6 V, unless otherwise noted) Symbol VOH VOH VOL VOL IIH Parameter "H" level output voltage P0, P1, P2, D0-D5 "H" level output voltage C, CNTR "L" level output voltage P0, P1, P2, D0-D7, C, CNTR "L" level output voltage RESET "H" level input current P0, P1, P2, D0-D5, XIN, XCIN, RESET CNTR, INT IIL "L" level input current P0, P1, P2, D0-D5, XIN, XCIN, RESET CNTR, INT RPU Pull-up resistor value VI = 0 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V 10 %, Ta = 25 C 100 0.4 0.3 0.2 250 400 17 V V V kHz % 50 120 250 k P0, P1, RESET VT+ - VT- Hysteresis RESET VT+ - VT- Hysteresis INT VT+ - VT- Hysteresis CNTR f(RING) On-chip oscillator clock frequency f(XIN) Frequency error (with RC oscillation, error of external R, C not included ) RCOM RSEG RVLC (Note 1) COM output impedance (Note 2) SEG output impedance (Note 2) Internal resistor for LCD power supply VDD = 3 V VDD = 3 V When dividing resistor 2r 3 selected When dividing resistor 2r 2 selected When dividing resistor r 3 selected When dividing resistor r 2 selected IDD VDD = 3 V Supply current at active mode (with a ceramic resonator) f(XIN) = 4 MHz f(RING) = stop f(XCIN) = stop at active mode (with an on-chip oscillator) VDD = 3 V f(XIN) = stop f(RING) = active f(XCIN) = stop at active mode (with a quartz-crystal oscillator) at clock operation mode (POF instruction execution) at RAM back-up mode (POF2 instruction execution) VDD = 3 V f(XIN) = stop f(RING) = stop f(XCIN) = 32 kHz VDD = 3 V f(XCIN) = 32 kHz Ta = 25 C VDD = 3 V f(STCK) = f(XIN)/8 f(STCK) = f(XIN)/4 f(STCK) = f(XIN)/2 f(STCK) = f(XIN) f(STCK) = f(RING)/8 f(STCK) = f(RING)/4 f(STCK) = f(RING)/2 f(STCK) = f(RING) f(STCK) = f(XCIN)/8 f(STCK) = f(XCIN)/4 f(STCK) = f(XCIN)/2 f(STCK) = f(XCIN) 300 200 150 100 2 2 480 320 240 160 0.3 0.4 0.6 0.9 12 17 27 48 5 6 7 9 5 0.1 10 10 960 640 480 320 0.6 0.8 1.2 1.8 24 34 54 96 10 12 14 18 10 2 6 mA k k k VI = 0 V P0, P1 No pull-up -2 VI = VDD 2 VDD = 3 V VDD = 3 V VDD = 3 V VDD = 3 V Test conditions IOH = -5 mA IOH = -1 mA IOH = -10 mA IOH = -3 mA IOL = 9 mA IOL = 3 mA IOL = 2 mA Limits Min. 2.1 2.4 2.1 2.4 1.4 0.9 0.9 V V Typ. Max. Unit V V
A
A
A
A
A A
Notes 1: When RC oscillation is used, use the external 33 pF capacitor (C). 2: The impedance state is the resistor value of the output voltage. at VLC3 level output: VO = 0.8 VLC3 at VLC2 level output: VO = 0.8 VLC2 at VLC1 level output: VO = 0.2 VLC2 + VLC1 at VSS level output: VO = 0.2 VSS
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 137 of 142
4556 Group
VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS
(One Time PROM version: Ta = -20 C to 85 C, unless otherwise noted) Symbol VRST- Parameter Detection voltage (reset occurs) (Note 2) Ta = 25 C -20 C Ta < 0 C 0 C Ta < 50 C 50 C Ta 85 C VRST+ Detection voltage (reset release) (Note 3) Ta = 25 C -20 C Ta < 0 C 0 C Ta < 50 C 50 C Ta 85 C VRST+ - VRST- IRST TRST Operation current (Note 4) Detection time (Note 5) VDD = 3 V VDD (VRST- - 0.1 V) 30 0.2 60 1.2 Detection voltage hysteresis Test conditions Min. 1.6 1.7 1.4 1.2 1.7 1.8 1.5 1.3 0.1 1.9 Limits Typ. 1.8 Max. 2 2.3 2.2 1.9 2.1 2.4 2.3 2 V V Unit V
A
ms
Notes 1: The voltage drop detection circuit is equipped with only the H version. 2: The detection voltage (VRST-) is defined as the voltage when reset occurs when the supply voltage (VDD) is falling. 3: The detection voltage (VRST+) is defined as the voltage when reset is released when the supply voltage (VDD) is rising from reset occurs. 4: In the H version, IRST is added to IDD (supply current). 5: The detection time (TRST) is defined as the time until reset occurs when the supply voltage (VDD) is falling to [VRST- - 0.1 V]. 6: The detection voltages (VRST+, VRST-) are set up lower than the minimum value of the supply voltage of the recommended operating conditions. As for details, refer to the LIST OF PRECAUTIONS.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 138 of 142
4556 Group
BASIC TIMING DIAGRAM
Parameter
Machine cycle Pin (signal) name
Mi
Mi+1
System clock
STCK
Port D output
D0-D7
Port D input
D0-D5
Ports P0, P1, P2 output
P00-P03 P10-P13 P20-P23
Ports P0, P1, P2 input P00-P03 P10-P13 P20-P23
Interrupt input
INT
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 139 of 142
4556 Group
BUILT-IN PROM VERSION
In addition to the mask ROM versions, the 4556 Group has the One Time PROM versions whose PROMs can only be written to and not be erased. The built-in PROM version has functions similar to those of the mask ROM versions, but it has PROM mode that enables writing to built-in PROM. Table 19 Product of built-in PROM version PROM size Part number ( 10 bits) M34556G8FP 8192 words M34556G8HFP
Table 19 shows the product of built-in PROM version. Figure 61 shows the pin configurations of built-in PROM versions. The One Time PROM version has pin-compatibility with the mask ROM version.
RAM size ( 4 bits) 288 words
Package 42P2R-A
ROM type One Time PROM [shipped in blank]
(1) PROM mode
The 4556 Group has a PROM mode in addition to a normal operation mode. It has a function to serially input/output the command codes, addresses, and data required for operation (e.g., read and program) on the built-in PROM using only a few pins. This mode can be selected by muddog entry after powering on the VDD pin. In the PROM mode, three types of software commands (read, program, and program verify) can be used. Clock-synchronous serial I/O is used, beginning from the LSB (LSB first).
Writing with PROM programmer
Screening (Leave at 150 C for 40 hours) (Note)
(2) Notes on handling
For the One Time PROM version shipped in blank, Renesas corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to improve reliability after writing, performing writing and test according to the flow shown in Figure 60 before using is recommended (Products shipped in blank: PROM contents is not written in factory when shipped).
Verify test with PROM programmer
Function test in target device Note: Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 C exceeding 100 hours.
Fig. 68 Flow of writing and test of the product shipped in blank
(3) Difference between Mask ROM version and One Time PROM version
Mask ROM version and One Time PROM version have some difference of the following characteristics within the limits of an electrical property by difference of a manufacture process, builtin ROM, and a layout pattern. * a characteristic value * a margin of operation * the amount of noise-proof * noise radiation, etc., Accordingly, be careful of them when swithcing.
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 140 of 142
4556 Group
PIN CONFIGURATION (TOP VIEW)
XIN XOUT VPP
XIN XOUT CNVSS XCIN/D6 XCOUT/D7
RESET
1 2 3 4 5 6 7 9 10 11 12 13 14 15 16 17 18 19 20 21 8
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
VSS VDD C/CNTR D5/INT D4 D3 D2 D1 D0
VSS VDD
RESET COM0 COM1 COM2 COM3 SEG0/VLC3 SEG1/VLC2 SEG2/VLC1 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10
M34556G8FP M34556G8HFP
P13/SEG28 P12/SEG27 P11/SEG26 P10/SEG25 P03/SEG24 P02/SEG23 P01/SEG22 P00/SEG21 P23/SEG20 P22/SEG19 P21/SEG18 P20/SEG17
PGM
VDD
VDD
SDA SCLK
Fig. 69 Pin configuration of built-in PROM version
ROM CODE ACCESS PROTECTION
We would like to support a simple ROM code protection function that prevents a party other than the ROM-code owner to read and reprogram the built-in PROM code of the MCU. First, Programmers must check the ID-code of the MCU. If the ID-code is not blank, Programmer verifies it with the input IDcode. When the ID-codes do not match, Programmer will reject all further operations. The MCU has each 10 bits of dedicated ROM spaces in address 009016 to 009616, as an ID-code (referred to as "the ID-code") enabling a Programmer to verify with the input ID-code and validate further operations.
Address 009016 009116 009216 009316 009416 009516 009616 009716 ID1 ID2 ID3 ID4 ID5 ID6 ID7
Fig. 70 ROM-Code Protection ID Location
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 141 of 142
4556 Group
PACKAGE OUTLINE
42P2R-A
EIAJ Package Code SSOP42-P-450-0.80
42
Recommended
JEDEC Code - Weight(g) 0.63
22
Plastic 42pin 450mil SSOP
Lead Material Alloy 42/Cu Alloy e b2
HE
E
e1
F
Recommended Mount Pad Dimension in Millimeters Min Nom Max 2.4 - - - - 0.05 - 2.0 - 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 - 0.8 - 12.23 11.93 11.63 0.7 0.5 0.3 - 1.765 - - 0.75 - - - 0.9 0.15 - - 0 - 10 - 0.5 - - 11.43 - - 1.27 -
Symbol
1 21
A
G
D
A2 e y
b
A1
A A1 A2 b c D E e HE L L1 z Z1 y b2 e1 I2
L1
c z Z1 Detail G Detail F
Rev.3.02 Dec 22, 2006 REJ03B0025-0302
page 142 of 142
L
I2
REVISION HISTORY
Rev. Date Page 1.00 Jul. 23, 2003 1.01 Sep. 17, 2003 - 50 51
4556 Group Data Sheet
Description Summary
First edition issued Voltage drop detection circuit (only in H version) revised. Table 15 revised. Timer functions, Timer control registers, Port level, and Notes 6 and 7) 19 Voltage drop detection circuit (only in H version) revised. 61 Fig.57 revised. 128 2.00 Feb. 24, 2004 FEATURES: 1 q Minimum instruction execution time: time for One Time PROM version added. q Supply voltage of One Time PROM version revised. PERFORMANCE OVERVIEW: 4 Minimum instruction execution time: time for One Time PROM version added. Supply voltage of One Time PROM version revised. Power dissipation: Values only for Mask ROM version are listed. Port block diagram (6): SEG17-SEG28 eliminated. 13 Table 9: Timer 3; Count source and Use of output signal revised. 29 (1) Power-on reset : "(only for H version)" eliminated. 48 Description revised. Fig.37: "(only for H version)" added to Voltage drop detection circuit. Fig.40: Note revised. 50 ROM ORDERING METHOD revised. 58 Note on 18 Power-on reset : revised. 61 120 to 132 ELECTRICAL CHARACTERISTICS revised. The table is separated to Mask ROM version and One Time PROM version. Supply voltage and supply current revised mainly. Note 6 is added to VOLTAGE DTOP DETECTION CIRCUIT CHARACTERISTICS. 3.00 Jul. 09, 2004 All pages 5 31 39 40 46 Words standardized: On-chip oscillator ____________ Description of RESET pin revised. Fig.23: Note added. Some description revised. Fig.28: "DI" instruction added. (5) LCD power supply circuit q Internal dividing resistor revised. Fig.34 d): "VLC3, VLC2, VLC1" added. Fig.35, Fig.36: Count revised. Fig.38: State of quartz-crystal oscillator added. Note on Power Source Voltage added. RECOMMENDED OPERATING CONDITIONS 1 VDD (RC oscillation) Max.: 3.6
47 49 61 128
(1/2)
REVISION HISTORY
Rev. Date Page
4556 Group Data Sheet
Description Summary
3.01 Jun.15, 2005 All pages Delete the following: "PRELIMINARY". 36 *Prescaler and Timer 1 count start timing and count time when operation starts, *Timer 2 and Timer LC count start timing and count time when operation starts added. 13 Prescaler and Timer 1 count start timing and count time when operation starts, 61 14 Timer and Timer LC count start timing and count time when operation starts added. 3.02 Dec. 22, 2006 29, 33 Use of output signal of prescaler: LC eliminated. 30, 31 Fig.22, Fig.23: Note added. 31 Fig.23: INSTCK (wrong) INTSNC (correct) 32, 69 PA0: Stop (state initialized) (state retained) W31 W30: Timer 3 count source selection bits Timer 3 count value selection bits 33 (2) Prescaler (interrupt function): PRS (wrong) RPS (correct) 34 (5) Timer 3 (interrupt function): Description added. 48 Fig.37: Clock (wrong) f(RING) (correct) 52 Table 15 Timer 3 function (RAM back-up): O (Note 3) Timer interrupt request flag (RAM back-up): O (Note 3) 54 Fig.44: Note 1 added. 55, 73 Table 17: Notes 2 and 3 added. 60 to 63 NOTES ON NOISE added. 64 Noise and latch-up prevention: Description added. 77, 120, SZD: (Y) = 0 to 7 0 to 5 121 93 SZD: Detailed description revised. 132 VRST-, VRST+: Test condition revised. 132, 138 Note 4: (power current) (supply current) Pages 16 to 18, 20, 27, 54, 66: RAM back-up mode power down mode Pages 77, 90 to 92, 116 to 119: SNZ0, SNZT1, SNZT2, SNZT3 revised. Pages 78, 109, 122, 123: WRST revised.
(2/2)
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Notes: 1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
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(c) 2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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